As transistor sizes continue shrinking, impacts of variability has become ever more paramount in circuit design and manufacturing. Their accurate representations in model cards help save design margins and provide appropriate guidelines in design technology co-optimization (DTCO). To address such a challenge, we propose a novel machine learning framework, Normalizing Flow-Based Joint Generative Model (NFGen), which generates a comprehensive model library from a limited number of model cards. Unlike traditional generative methods that focus on the marginal distribution of model card parameters, NFGen is the first model to approximate their joint distribution, which includes information on their correlation and thus enables closer representation of variability effects. In addition, we introduce two similarity metrics to rigorously evaluate the quality of generated model cards. Experimental results show that NFGen reduces overall error by 2x to 8x compared to state-of-the-art methods, validating its superiority in variability-aware DTCO.

Yield estimation and optimization is ubiquitous in modern circuit design but remains elusive for large-scale chips. This is largely due to the mounting cost of transistor-level simulation and one's often limited resources. In this study, we propose a novel framework to estimate and optimize yield using Bayesian Neural Network (BNN-YEO). By coupling machine learning method with Bayesian network, our approach can effectively integrate prior knowledge and is unaffected by the overfitting problem prevalent in most surrogate models. With the introduction of a smooth approximation of the indicator function, it incorporates gradient information to facilitate global yield optimization. We examine its effectiveness via numerical experiments on 6T SRAM and found that BNN-YEO provides 100x speedup (in terms of SPICE simulations) over standard Monte Carlo in yield estimation, and 20x faster than the state-of-the-art method for total yield estimation and optimization with improved accuracy.