Tree-based model editors and hybrid graphical-textual model editors have advantages and limitations when editing domain models. Data is displayed hierarchically in tree-based model editors, whereas hybrid graphical-textual model editors capture high-level domain concepts graphically and low-level domain details textually. We conducted an empirical user study with 22 participants to evaluate the implicit assumption of system modellers that hybrid notations are superior, and to investigate the tradeoffs between the default EMF-based tree model editor and a Sirius/Xtext-based hybrid model editor. The results of the user study indicate that users largely prefer the hybrid editor and are more confident with hybrid notations for understanding the meaning of conditions. Furthermore, we found that the tree editor provided superior performance for analysing ordered lists of model elements, whereas activities requiring the comprehension or modelling of complex conditions were carried out faster through the hybrid editor.

Abstract Multi-robot systems are increasingly deployed to provide services and accomplish missions whose complexity or cost is too high for a single robot to achieve on its own. Although multi-robot systems offer increased reliability via redundancy and enable the execution of more challenging missions, engineering these systems is very complex. This complexity affects not only the architecture modelling of the robotic team but also the modelling and analysis of the collaborative intelligence enabling the team to complete its mission. Existing approaches for the development of multi-robot applications do not provide a systematic mechanism for capturing these aspects and assessing the robustness of multi-robot systems. We address this gap by introducing ATLAS, a novel model-driven approach supporting the systematic design space exploration and robustness analysis of multi-robot systems in simulation. The ATLAS domain-specific language enables modelling the architecture of the robotic team and its mission and facilitates the specification of the team’s intelligence. We evaluate ATLAS and demonstrate its effectiveness in three simulated case studies: a healthcare Turtlebot-based mission and two unmanned underwater vehicle missions developed using the Gazebo/ROS and MOOS-IvP robotic platforms, respectively.

Multi-robot systems are increasingly deployed to provide services and accomplish missions whose complexity or cost is too high for a single robot to achieve on its own. Although multi-robot systems offer increased reliability via redundancy and enable the execution of more challenging missions, engineering these systems is very complex. This complexity affects not only the architecture modelling of the robotic team but also the modelling and analysis of the collaborative intelligence enabling the team to complete its mission. Existing approaches for the development of multi-robot applications do not provide a systematic mechanism for capturing these aspects and assessing the robustness of multi-robot systems. We address this gap by introducing ATLAS, a novel model-driven approach supporting the systematic robustness analysis of multi-robot systems in sim-illation. The ATLAS domain-specific language enables modelling the architecture of the robotic team and its mission, and facilitates the specification of the team's intelligence. We evaluate ATLAS and demonstrate its effectiveness on two oceanic exploration missions performed by a team of unmanned underwater vehicles developed using the MOOS-IvP robotic simulator.

This article describes the motivation, design, analysis, and configuration of the criticality-aware multi-hop wireless communication protocol AirTight. Wireless communication has become a crucial part of the infrastructure of many cyber-physical applications. Many of these applications are real-time and also mixed-criticality, in that they have components/subsystems with different consequences of failure. Wireless communication is inevitably subject to levels of external interference. In this article, we represent this interference using a criticality-aware fault model; for each level of temporal interference in the fault model, we guarantee the timing behaviour of the protocol (i.e., we guarantee that packet deadlines are satisfied for certain levels of criticality). Although a new protocol, AirTight is built upon existing standards such as IEEE 802.15.4. A prototype implementation and protocol-accurate simulator have been produced. This article develops a series of schedulability analysis techniques for single-channel and multichannel wireless Cyber-Physical Systems (CPS). Heuristics are specified and evaluated as the starting point of design space exploration. Genetic algorithms are then defined and evaluated to assess their performance in developing schedule tables incorporating multichannel allocations in these systems.

This paper describes the motivation, design, analysis and implementation of a new protocol for critical wireless communication called AirTight. Wireless communication has become a crucial part of the infrastructure of many cyber-physical applications. Many of these applications are real-time and also mixed-criticality, in that they have components/subsystems with different consequences of failure. Wireless communication is inevitably subject to levels of external interference. In this paper we represent this interference using a criticality-aware fault model; for each level of interference in the fault model we guarantee the timing behaviour of the protocol (i.e. we guarantee that packet deadlines are satisfied for certainly levels of criticality). Although a new protocol, AirTight is built upon existing standards such as IEEE 802.15.4. A prototype implementation and protocol-accurate simulator, which are also built upon existing technologies, demonstrate the effectiveness and functionality of the protocol.

Mixed-criticality applications executing over a multiprocessor platform based on Network-on-Chip (NoC) exchange packets of different criticality levels through the same communication infrastructure, and transmission of a packet has potential impact over the latency of all the others. This paper presents NoC architectural improvements to output port arbitration and mode change signalling. The first aim is to improve the average latency of low-criticality packets following a mode change by allowing NoC arbiters to service them during cycles in which no high-criticality flows can be transmitted. The second aim is to reduce the worst-case latency of high-criticality packets transmitted by the NoC. The former objective improves the system's responsiveness, while the latter contributes to increased resource efficiency. The achieved improvements are evaluated, respectively, by cycle-accurate simulation and by schedulability analysis, showing full delivery of low-criticality packets following a criticality change, and achieving full schedulability in 8.2% more flow sets than the state of the art.

Arbitration policies and predictability enhancement measures typically employ packet priority as the decisive parameter. Though packet timeliness is a key attribute, Network-on-Chip designs rarely consider timeliness as a parameter mostly due to the impracticality of utilising time stamping which relay on the notion of a global time. In this paper, we introduce a low overhead approach where packets carry a slack value, which would notify the router of the latency the packet can suffer without any adverse effects. This would enable routers to service late packets (even lower priority ones) by trading the expendable time associated with the high priority packets hence improving overall quality of service. Utilising a Hardware Description Language coded prototype, we demonstrate the effectiveness of the technique and quantify the associated hardware overhead.

An increasingly time-consuming part of the design flow of on-chip multiprocessors is the simulation of the interconnect architecture. The accurate simulation of state-of-the art network-on-chip interconnects can take hours, and this process is repeated for each design iteration because it provides valuable insights on communication latencies that can greatly affect the overall performance of the system. In this article, we identify a time-predictable network-on-chip architecture and show that its timing behaviour can be predicted using models which are far less complex than the architecture itself. We then explore such a feature to produce simplified and lightweight simulation models that can produce latency figures with more than 90% accuracy and simulate more than 1,000 times faster when compared to a cycle-accurate model of the same interconnect.

Lack of scalability and difficulties in predicting the temporal behaviour of bus-based architectures has lead to the development of Network-on-Chip (NoC) protocols that provide a schedulable resource for moving data across multi-core platforms. Wormhole switching and credit-based flow control protocols have been used to support flit-level priority-preemptive link arbitration in NoCs, which leads to analysable temporal behaviour. In this paper we develop a new protocol (WPMC), based on the same family of protocols, that gives full support to mixed-criticality on-chip communications. WPMC is defined to give adequate partitioning between criticality levels, and to use resources efficiently. Analysis is developed and implementation aspects are considered. A cycle accurate simulator is used for scenario-based verification, and the effectiveness of the protocol and its scheduling model is evaluated via message-set generation.