CC-TEGAS3 is a digital logic simulation system containing subsystems which can perform three different modes of simulation. These modes are used for logic or design verification, worst case timing analysis, and fault simulation. The basic device models are for Boolean gates, a wide range of flip-flops and latches, and a number of MOS elements such as transfer gates. A comprehensive list of functional level device models were incorporated into the system and the resulting system is called CC-TEGAS4. This approach was considered advantageous for today's technology, and an absolute necessity for the LSI and VLSI technologies that are forthcoming. This paper is concerned with the problems encountered and some of the techniques used to implement these functional level models, and results obtained in terms of reduction in required computer resources needed to simulate a network utilizing these new models.

This paper describes the basic data structures and algorithms for a functional level fault simulator. The technique used is that of concurrent fault simulation. The algorithms and data structure support multi-signal value, gate and functional level device models. These algorithms and data structures also support the capability to simulate user defined faults and faults that cause timing violations. In the experimental version of the system, developed at the University of Texas, only classical stuck-at faults and faults that lead to timing discrepancies between the good and the faulty circuit were implemented. Minor additions to the data structures will allow the simulator to process non-classical faults like: (1) memory stuck-at, (2) user defined functional faults, (3) technology dependent shorted signal faults, etc. The accuracy achieved simulating a fault is consistent with the accuracy of the non-fault model.

There are many activities included under the category of design automation for integrated circuits. Some of these activities include packaging, placement, routing, interactive graphics, device data bases, and digital simulation; for the purpose of logic verification, timing analysis, and diagnostic test verification. One might also include high-level simulation, such as register transfer simulation, for the purpose of initial logic verification. This paper will be oriented towards modeling and implementation questions which arise when one is attempting to implement an extremely accurate digital simulator for the purposes of logic and design verification and fault simulation. Simulators for these purposes are now extremely important and occupy a major role in any design automation system. These systems are also very expensive and therefore the incorrect answers to a variety of questions which arise during the process of developing such simulators can be disastrous. This paper shall attempt to acquaint the reader with questions that have arisen over the years in terms of developing these simulators and what some of the possible answers are, and their respective tradeoffs. Although the successes, and, equally the failures, of many people have contributed to the present state of the art of digital simulators, one particular simulator, the one the authors are most intimately involved with, will be used as a source of detailed examples demonstrating many of the questions to be discussed.