VLDB 2026 Research / reviewers in the wild / expert
Der-Cheng Huang
dblp:39/1273
· DBLP profile ↗
5ranked-venue papers
3as first author
0since 2021 · last 2002
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 5 · 3 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware verification and test |
0.1 | 2 | 2002 | A parallel transparent BIST method for embedded memory arrays bytolerating redundant operations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002 A parallel built-in self-diagnostic method for embedded memoryarrays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002 |
Electronic design automation › hardware verification and test › memory testing
march test algorithm |
0.1 | 2 | 2002 | A parallel transparent BIST method for embedded memory arrays bytolerating redundant operations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002 A parallel built-in self-diagnostic method for embedded memoryarrays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002 |
Electronic design automation › hardware verification and test › design for testability › built-in self-test
memory BIST |
0.1 | 2 | 2002 | A parallel transparent BIST method for embedded memory arrays bytolerating redundant operations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002 A parallel built-in self-diagnostic method for embedded memoryarrays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002 |
Electronic design automation › hardware verification and test
memory testing |
0.1 | 2 | 2002 | A parallel transparent BIST method for embedded memory arrays bytolerating redundant operations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002 A parallel built-in self-diagnostic method for embedded memoryarrays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002 |
Electronic design automation › hardware test
built-in self-diagnosis |
0.0 | 1 | 2002 | A parallel built-in self-diagnostic method for embedded memoryarrays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002 |
Methods — techniques the papers use, named apart from their topics
circular scan test interface · 0.0bidirectional serial interfacing · 0.0TRSMarch · 0.0DiagRSMarch · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2002 | A parallel built-in self-diagnostic method for embedded memoryarraysabstractIn this paper, the authors propose a new built-in self-diagnosis method to simultaneously diagnose spatially distributed memory modules with different sizes. Based on the serial interfacing technique, the serial fault masking effect is observed and a bidirectional serial interfacing technique is proposed to deal with such an issue. By tolerating redundant read/write operations, they develop a new march algorithm called DiagRSMarch to achieve the goals of low test signal routing overhead, tolerable diagnostic time, and high diagnostic coverage. It can be proved that DiagRSMarch can identify all stuck-at, transition, state coupling, and dynamic coupling faults occurring in all memory arrays. Experimental results also demonstrate that the test efficiency of DiagRSMarch is highly dependent on memory topology, defect-type distribution, and degree of parallelism. Der-Cheng Huang, Wen-Ben Jone |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2002 | A parallel transparent BIST method for embedded memory arrays bytolerating redundant operationsabstractIn this paper, the authors propose a new transparent built-in self-test method to test in parallel multiple embedded memory arrays with various sizes. First, a new transparent test interface is designed to perform testing in the normal mode and to cope with test interrupts in a real-time manner. The circular scan test interface facilitates the processes of both test pattern generation and signature analysis. By tolerating redundant read/write/shift operations, we develop a new march algorithm called TRSMarch to achieve the goals of low hardware overhead, short test time, and high fault coverage. It can be proved that TRSMarch can detect all stuck-at faults, all transition faults, and each coupling fault occurring in different words. For each coupling fault occurring in the same word, depending on the coupling type and effect, it can be detected or its detection probability can be high as more transparent processes are executed. TRSMarch can be easily extended to deal with more faults such as single-cell read destructive faults and read destructive coupling faults. Der-Cheng Huang, Wen-Ben Jone |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2002 | An efficient BIST method for distributed small buffersabstractIn this work, we propose a new built-in self-testing (BIST) method that is able to concurrently test a set of spatially distributed embedded-memory modules with different sizes. Using the concept of redundant read-write operations, we develop a new march method, called RSMarch, to efficiently test each memory module. The new method has the advantages of low hardware overhead, short test time, and high-fault coverage. The total test time is dominated by large-size modules. To further reduce the test time, we also propose a split-mode test method to virtually partition each large memory array into smaller modules, which can be tested simultaneously. Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee |
IEEE Trans. Very Large Scale Integr. Syst. | 2 |
| 2000 | An efficient parallel transparent diagnostic BISTabstractIn this paper, we propose a new transparent Built-in Self-Diagnosis (BISD) method to diagnose multiple embedded memory arrays with various sizes in parallel. A new transparent diagnostic interface has been proposed to perform testing in normal mode. By tolerating redundant read/write/shift operations, we develop a new march algorithm called TDiagRSMarch to achieve the goals of low hardware overhead, lower test time, and high test coverage. Experimental results demonstrate that the diagnostic efficiency of TDiagRSMarch is independent of memory topology, defect-type distribution, and degree of parallelism. Der-Cheng Huang, Wen-Ben Jone |
Asian Test Symposium | 1 |
| 1999 | An Efficient BIST Method for Small BuffersabstractIn this work, we propose a new built-in self-testing (BIST) method that is able to concurrently test a set of spatially distributed embedded-memory modules with different sizes. By allowing some redundant read/write operations for small modules, we develop a new march algorithm, called RSMarch, that can concurrently test all memory modules with the same fault coverage as if each module is tested individually. We also show that this method requires only one simple BIST controller and one test data line for all modules. Thus the new method has the advantages of short test time, high fault coverage and low area overhead. Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee |
VTS | 2 |