Precise estimation of correlation or similarity between two random variables lies at the heart of signal detection, target localization and pattern recognition. In this paper, we show that there exists a large class of multiplier-less analog correlators that can demonstrate a higher signal-to-noise ratio (SNR) compared to a conventional multiply-accumulate (MAC) based correlator. The multiplier-less design uses a Margin Propagation (MP) principle combining rectifying diodes in a symmetric circuit architecture. Using Price’s theorem we present a novel analytical framework that can be used to understand the steady-state behavioral response of different MP correlator circuits. The analytical results have been verified using transient and steady-state circuit simulations of correlator circuits designed in a standard CMOS process.

Decoding of Low-Density Parity Check (LDPC) codes can be viewed as a special case of XOR-SAT problems, for which low-computational complexity bit-flipping algorithms have been proposed in the literature. However, a performance gap exists between the bit-flipping LDPC decoding algorithms and the benchmark LDPC decoding algorithms, such as the Sum-Product Algorithm (SPA). In this paper, we propose an XOR-SAT solver using log-sum-exponential functions and demonstrate its advantages for LDPC decoding. This is then approximated using the Margin Propagation formulation to attain a low-complexity LDPC decoder. The proposed algorithm uses soft information to decide the bit-flips that maximize the number of parity check constraints satisfied over an optimization function. The proposed solver can achieve results that are within 0.1dB of the Sum-Product Algorithm for the same number of code iterations. It is also at least$10 \times $lower than other Gradient-Descent Bit Flipping decoding algorithms, which are also bit-flipping algorithms based on optimization functions. The approximation using the Margin Propagation formulation does not require any multipliers, resulting in significantly lower computational complexity than other soft-decision Bit-Flipping LDPC decoders.

Recent advances in margin-propagation (MP) based approximate computing have resulted in analog computing circuits that exhibit scaling properties similar to that of digital computing circuits. MP-based circuits allow trading off energy-efficiency with speed and precision, endow robustness to temperature variations, and make the design portable across different process nodes. In this work, We leverage these scaling properties to design ARYABHAT, a field-programmable analog machine learning processor that can be synthesized like digital field-programmable gate arrays (FPGAs). ARYABHAT features a fully reconfigurable tile-based modular analog architecture with adjustable throughput and configurable energy requirements, making it suitable for various machine-learning computations. The architecture can perform computations at variable accuracy and different power-performance specifications and can simultaneously leverage near-memory computing paradigms to improve computational throughput. We also present a complete programming and test ecosystem for ARYABHAT called ARYAFlow and ARYATest. As proof of concept, we showcase the implementation of machine learning algorithms at different performance specifications.

At the fundamental level, an energy imbalance exists between training and inference in machine learning (ML) systems. While inference involves recall using a fixed or learned set of parameters that can be energy-optimized using compression and sparsification techniques, training involves searching over the entire set of parameters and hence requires repeated memorization, caching, pruning, and annealing. In this paper, we introduce three “performance walls” that determine the training energy efficiency, namely, the memory-wall, the update-wall, and the consolidation-wall. While the emerging compute-in-memory ML architectures can address the memory-wall bottleneck (or energy-dissipated due to repeated memory access) the approach is agnostic to energy-dissipated due to the number and precision required for the training updates (the update-wall) and is agnostic to the energy-dissipated when transferring information between short-term and long-term memories (the consolidation-wall). To overcome these performance walls, we propose a learning-in-memory (LIM) paradigm that prescribes ML system memories with metaplasticity and whose thermodynamical properties match the physics and energetics of learning.

Analog computing is attractive compared to digital computing due to its potential for achieving higher computational density and higher energy efficiency. However, unlike digital circuits, conventional analog computing circuits cannot be easily mapped across different process nodes due to differences in transistor biasing regimes, temperature variations and limited dynamic range. In this work, we generalize the previously reported margin-propagation-based analog computing framework for designing novel shape-based analog computing (S-AC) circuits that can be easily cross-mapped across different process nodes. Similar to digital designs S-AC designs can also be scaled for precision, speed, and power. As a proof-of-concept, we show several examples of S-AC circuits implementing mathematical functions that are commonly used in machine learning architectures. Using circuit simulations we demonstrate that the circuit input/output characteristics remain robust when mapped from a planar CMOS 180nm process to a FinFET 7nm process. Also, using benchmark datasets we demonstrate that the classification accuracy of a S-AC based neural network remains robust when mapped across the two processes and to changes in temperature.

Long-term monitoring and tracking of wildlife and endangered species in their natural environment is challenging due to human factors and logistical limitations. We present a light-weight, always-on acoustic classification system that can identify the density of specific wildlife species in an ecological environment where human presence may be undesirable. The system uses a template-based support-vector-machine (SVM) classifier that combines acoustic filtering and classification into an in-filter computing and a hardware-friendly platform. We demonstrate the system’s capabilities for identifying the density of different bird species using ARM Cortex-M4 based AudioMoth hardware. The embedded software, designed specifically for the AudioMoth hardware, can generate the programmable parameters, given limited training samples corresponding to different wildlife species. We show that the system can identify four different bird species with an accuracy of more than 95% and consumes a memory footprint of 14 KB SRAM and 149 KB Flash memory that can run for 48 days on battery without any human intervention.

We present a novel in-filter computing framework that can be used for designing ultralight acoustic classifiers for use in the smart Internet of Things (IoT). Unlike a conventional acoustic pattern recognizer, where the feature extraction and classification are designed independently, the proposed architecture integrates the convolution and nonlinear filtering operations directly into the kernels of a support vector machine (SVM). The result of this integration is a template-based SVM whose memory and computational footprint (training and inference) is light enough to be implemented on a field-programmable gate array (FPGA)-based IoT platform. While the proposed in-filter computing framework is general enough, in this article, we demonstrate this concept using a cascade of an asymmetric resonator with inner hair cells (CAR-IHCs)-based acoustic feature extraction algorithm. The complete system has been optimized using time-multiplexing and parallel-pipeline techniques for a Xilinx Spartan 7 series FPGA. We show that the system can achieve robust classification performance on benchmark sound recognition tasks using only 1.5k lookup tables (LUTs) and 2.8k flip-flops (FFs), a significant improvement over other approaches.

In this paper, we propose a novel class of symmetric key distribution protocol that leverages basic security primitives offered by low-cost, hardware chipsets containing millions of synchronized self-powered timers. The keys are derived from the temporal dynamics of a physical, micro-scale time-keeping device which makes the keys immune to any potential side-channel attacks, malicious tampering, or snooping. Using the behavioral model of the self-powered timers, we first show that the derived key-strings can pass the randomness test as defined by the National Institute of Standards and Technology (NIST) suite. The key-strings are then used in two SPoTKD (Self-Powered Timer Key Distribution) protocols that exploit the timer’s dynamics as one-way functions: (a) protocol 1 facilitates secure communications between a user and a remote Server; and (b) protocol 2 facilitates secure communications between two users. In this paper, we investigate the security of these protocols under standard model and against different adversarial attacks. Using Monte-Carlo simulations, we also investigate the robustness of these protocols in the presence of real-world operating conditions and propose error-correcting SPoTKD protocols to mitigate these noise-related artifacts.

We present a novel framework for designing multiplierless kernel machines that can be used on resource-constrained platforms such as intelligent edge devices. The framework uses a piecewise linear (PWL) approximation based on a margin propagation (MP) technique and uses only addition/subtraction, shift, comparison, and register underflow/overflow operations. We propose a hardware-friendly MP-based inference and online training algorithm that has been optimized for a field-programmable gate array (FPGA) platform. Our FPGA implementation eliminates the need for digital signal processor (DSP) units and reduces the number of Look-Up Tables (LUTs). By reusing the same hardware for inference and training, we show that the platform can overcome classification errors and local minima artifacts that result from MP approximation. The implementation of this proposed multiplierless MP-kernel machine on FPGA results in an estimated energy consumption of 13.4 pJ and power consumption of 107 mW with ~9 k LUTs and Flip Flops (FFs) each for a 256 $\times $ 32 sized kernel making it superior in terms of power, performance, and area compared with other comparable implementations.

Traditional energy-based learning models associate a single energy metric to each configuration of variables involved in the underlying optimization process. Such models associate the lowest energy state with the optimal configuration of variables under consideration and are thus inherently dissipative. In this article, we propose an energy-efficient learning framework that exploits structural and functional similarities between a machine-learning network and a general electrical network satisfying Tellegen's theorem. In contrast to the standard energy-based models, the proposed formulation associates two energy components, namely, active and reactive energy with the network. The formulation ensures that the network's active power is dissipated only during the process of learning, whereas the reactive power is maintained to be zero at all times. As a result, in steady state, the learned parameters are stored and self-sustained by electrical resonance determined by the network's nodal inductances and capacitances. Based on this approach, this article introduces three novel concepts: 1) a learning framework where the network's active-power dissipation is used as a regularization for a learning objective function that is subjected to zero total reactive-power constraint; 2) a dynamical system based on complex-domain, continuous-time growth transforms that optimizes the learning objective function and drives the network toward electrical resonance under steady-state operation; and 3) an annealing procedure that controls the tradeoff between active-power dissipation and the speed of convergence. As a representative example, we show how the proposed framework can be used for designing resonant support vector machines (SVMs), where the support vectors correspond to an LC network with self-sustained oscillations. We also show that this resonant network dissipates less active power compared with its non-resonant counterpart.

Conventional approaches for wireless power transfer rely on the mutual coupling (near-field or far-field) between the transmitter and receiver transducers. As a result, the power-transfer efficiency of these approaches scales non-linearly with the cross-sectional area of the transducers and with the relative distance and respective alignment between the transducers. In this paper we show that when the operational power-budget requirements are in the order of microwatts, a self-capacitance (SC) based power delivery has significant advantages in terms of power transfer-efficiency (PTE), receiver form-factor and system scalability when compared to other modes of wireless power transfer (WPT) methods. We present a simple and a tractable equivalent circuit model that can be used to study the effect of different parameters on the SC-based WPT. In this paper we have experimentally verified the validity of the circuit using a cadaver mouse model. We also demonstrate the feasibility of a hybrid telemetry system where the microwatts of power that can be harvested from SC-based WPT approach is used for back-scattering a radio-frequency signal and is used for remote sensing of in-vivo physiological parameters like temperature. The functionality of the hybrid system has also been verified using a cadaver mouse model housed in a cage that was retrofitted with 915 MHz RF back-scattering antennas. We believe that the proposed remote power-delivery and hybrid telemetry approach would be useful in remote activation of wearable devices and in the design of energy-efficient animal cages used for long-term monitoring applications.

Self-powered clocks and time-keeping devices provide an ability to synchronize events across passive internet-of-things and tags that are spatially separated from each other. In this regard, Fowler-Nordheim tunneling based self-powered timers have been shown to reliably track time with an operating life-cycle greater than 2 years. However, the synchronization accuracy of a single FN-timer is determined by the variations in timer-device artifacts which could only be partially mitigated using ensemble averaging. In this paper, we propose a novel capacitively coupled network of FN-tunneling timers that can significantly improve the accuracy in presence of both timer-device and coupling capacitor mismatch. Using Monte-carlo simulations, we show that by choosing an appropriate size of the coupled network, the synchronization accuracy of the timekeeping device can be increased by a factor of 20dB.

Dynamical systems that evolve unidirectionally with respect to time provide a natural mechanism for implementing a time-domain, near-zero-threshold energy rectifier. In this paper we implement such a dynamical system using a pair of differential, leaky floating-gates and demonstrate that the circuit can sense and record signals of interest while compensating for environmental variations. A Fowler-Nordheim (FN) tunneling current has been used to implement the leakage process, which we experimentally show can be modulated by signals at energy levels below femtojoules. At this level of energy, the proposed FN-system could be self-powered using different types of biopotential energy sources like intra-cellular potentials, a feature that was not possible with previously reported recorders. Furthermore, the degree of modulation is shown to be a function of the input intensity as well as time-of-occurrence, which opens up the possibility of using reconstruction techniques to reconstruct the input signal from measurement of multiple sensing devices. Using devices fabricated in a 0.5 μm standard CMOS process, we demonstrate recording of 6 mV events with retention capability lasting over 30 minutes.

The ability to precisely synchronize and desynchronize two spatially separated dynamical systems according to changes in their respective operating environment provides a powerful mechanism for authentication and trust verification in a supply chain. This paper explores the synchronization and desynchronization paradigm using our previously reported self-powered time-keeping device, to differentiate among passive Internet-of-Things (IoT) devices that were subjected to different variations in temperature or their ambient radio-frequency environment. The environmental variations were modeled as a modulation voltage that affects the rate of Fowler-Nordheim (FN) quantum tunneling and integration of electrons on a floating-gate, thus producing a time and history-dependent dynamic signature. We show that the operation of the self-powered FN device is reliable and repeatable even at single electron-per-second tunneling-rates and for durations greater than three years. We believe that the proposed solution could be cost-effective and scalable for authenticating different types of passive IoT ranging from credit cards, packaged chipsets, to pharmaceuticals.

Autonomous, continuous and long-term monitoring systems are required to prognosticate failures in civil infrastructures due to material fatigue or extreme events like earthquakes. While current battery-powered wireless sensors can evaluate the condition of the structure at a given instant of time, they require frequent replacement of batteries due to the need for continuous or frequent sampling. On the other hand, self-powered sensors can continuously monitor the structural condition without the need for any maintenance; however, the scarcity of harvested power limits the range at which the sensors could be wirelessly interrogated. In this paper, we propose a quasi-self-powered sensor that combines the benefits of self-powered sensing and with the benefits of battery-powered wireless transmission. By optimizing both of the functionalities, a complete sensor system can be designed that can continuously operate between the structure's maintenance life-cycles and can be wirelessly interrogated at distances that obviates the need for taking the structure out-of-service. As a case study, in this paper we present the design considerations involved in prototyping quasi-self-powered sensors for deployment on the Mackinac Bridge in northern Michigan, with a target operational life span greater than 20 years.

The proliferation of passive Internet-of-Things (IoT) into the consumer and the enterprise market has necessitated enhanced security requirements. Many security protocols have been proposed in literature to address these requirements, however, they are either prone to certain types of attacks or are computationally expensive for resource- constrained passive IoT devices. In this paper we propose two variants of a novel mutual authentication protocol that utilizes the synchronization property of Fowler Nordheim (FN) tunneling based self-powered timers. The first protocol provides mutual authentication using the dynamic timer values. The protocol is both lightweight and provably immune to most of the well-known security attacks. Moreover, it offers an efficient and secure capability for easy revocation of tags and readers from the IoT system. The second protocol, an enhanced version of the first, provides disguised identities for applications that require privacy preserving. This protocol can thus serve as a perfect candidate for high-security passive IoT applications such as e- passports.

Passive Internet of Things (IoT) like radio frequency identification (RFID) tags can be used to offer a wide range of services, such as object tracking or classification, marking ownership, noting boundaries, and indicating identities. While the communication link between a reader of the tag and the authentication server is generally assumed to be secure, the communication link between the reader and participating tags is mostly vulnerable to malicious acts. Many authentication protocols have been proposed in literature, however, they either are vulnerable to certain types of attacks or require prohibitively a large amount of computational resources to be implemented on a passive tag. In this paper, we present variants of a novel authentication protocol that can overcome the security flaws of previous protocols while being well suited to the computational capability of the tags. At the core of the proposed approach is our recently demonstrated self-powered timing devices that can be used for robust time-keeping and synchronization without the need for any external powering. The outputs of the timers are processed using a single hash function on the tag to produce tokens that continuously change with time, while being synchronized to tokens generated by the authentication server. The proposed protocol also incorporates margins of tolerance that make the authentication process robust to any deviations in the timer responses due to fabrication artifacts.

Conservation principles, such as conservation of charge, energy, or mass, provide a natural way to couple and constrain spatially separated variables. In this paper, we propose a dynamical system model that exploits these constraints for solving nonconvex and discrete global optimization problems. Unlike the traditional simulated annealing or quantum annealing-based global optimization techniques, the proposed method optimizes a target objective function by continuously evolving a driver functional over a conservation manifold, using a generalized variant of growth transformations. As a result, the driver functional asymptotically converges toward a Dirac-delta function that is centered at the global optimum of the target objective function. In this paper, we provide an outline of the proof of convergence for the dynamical system model and investigate different properties of the model using a benchmark nonlinear optimization problem. Also, we demonstrate how a discrete variant of the proposed dynamical system can be used for implementing decentralized optimization algorithms, where an ensemble of spatially separated entities (for example, biological cells or simple computational units) can collectively implement specific functions, such as winner-take-all and ranking, by exchanging signals only with its immediate substrate or environment. The proposed dynamical system model could potentially be used to implement continuous-time optimizers, annealers, and neural networks.

This paper investigates the dynamical properties of a network of neurons, each of which implements an asynchronous mapping based on polynomial growth transforms. In the first part of this paper, we present a geometric approach for visualizing the dynamics of the network where each of the neurons traverses a trajectory in a dual optimization space, whereas the network itself traverses a trajectory in an equivalent primal optimization space. We show that as the network learns to solve basic classification tasks, different choices of primal-dual mapping produce unique but interpretable neural dynamics like noise shaping, spiking, and bursting. While the proposed framework is general enough, in this paper, we demonstrate its use for designing support vector machines (SVMs) that exhibit noise-shaping properties similar to those of modulators, and for designing SVMs that learn to encode information using spikes and bursts. It is demonstrated that the emergent switching, spiking, and burst dynamics produced by each neuron encodes its respective margin of separation from a classification hyperplane whose parameters are encoded by the network population dynamics. We believe that the proposed growth transform neuron model and the underlying geometric framework could serve as an important tool to connect well-established machine learning algorithms like SVMs to neuromorphic principles like spiking, bursting, population encoding, and noise shaping.

Growth transformations constitute a class of fixed-point multiplicative update algorithms that were originally proposed for optimizing polynomial and rational functions over a domain of probability measures. In this paper, we extend this framework to the domain of bounded real variables which can be applied towards optimizing the dual cost function of a generic support vector machine (SVM). The approach can, therefore, not only be used to train traditional soft-margin binary SVMs, one-class SVMs, and probabilistic SVMs but can also be used to design novel variants of SVMs with different types of convex and quasi-convex loss functions. In this paper, we propose an efficient training algorithm based on polynomial growth transforms, and compare and contrast the properties of different SVM variants using several synthetic and benchmark data sets. The preliminary experiments show that the proposed multiplicative update algorithm is more scalable and yields better convergence compared to standard quadratic and nonlinear programming solvers. While the formulation and the underlying algorithms have been validated in this paper only for SVM-based learning, the proposed approach is general and can be applied to a wide variety of optimization problems and statistical learning models.

Ambient infrasound with frequency ranges well below 20 Hz is known to carry robust navigation cues that can be exploited to authenticate the location of a speaker. Unfortunately, many of the mobile devices like smartphones have been optimized to work in the human auditory range, thereby suppressing information in the infrasonic region. In this paper, we show that these ultra-low frequency cues can still be extracted from a standard smartphone recording by using acceleration-based cepstral features. To validate our claim, we have collected smartphone recordings from more than 30 different scenes and used the cues for scene fingerprinting. We report scene recognition rates in excess of 90% and a feature set analysis reveals the importance of the infrasonic signatures towards achieving the state-of-the-art recognition performance.

In this paper we propose a novel approach for designing digital circuits that uses the variance of a signal to represent Boolean logic levels. The variance-based logic (VBL) representation enables embedding of rectification and multiplication modules within the basic logic cells and unlike AC-coupled or energy-recovery logic circuits the proposed approach obviates the need for any phase synchronization. As a result, VBL representation can be used for designing low-latency digital circuits that are directly powered by a combination of energy transducers with different frequency and source impedance characteristics. We present some representative examples of VBL circuits that can be implemented in a standard CMOS process and we present measurement results from fabricated prototype.

Summary form only given. Growth transform neuron models provide a neuromorphic approach for implementing well established machine learning algorithms while producing neural and population dynamics similar to what have been observed in biology, for example, spiking, bursting and noise-shaping [1]. In this demonstration, we will show some of these dynamics in real-time using an FPGA based acceleration platform that implements a network of growth transform neurons. The demonstration setup (Fig 1) will consist of a custom printed circuit board (PCB) that will interface to a laptop display for real-time display. The PCB will host a USB module, a Spartan 6 field programmable gate array (FPGA), and a VGA adaptor such that it will be possible to output the VGA signal to an external monitor. The FPGA will implement the spiking support vector machine (SVM) using growth transform neuron models in the same manner as described in the appended paper. The inputs to the FPGA will include the network interconnection (synaptic) matrix and will correspond to a SVM kernel matrix. These parameters can be programmed using a laptop as shown in Fig.1.

Cyborg insects provide a unique platform to implement autonomous robotics on a large scale. Compared to vertebrates, insect cyborgs can be deployed in swarms and at a significantly lower cost. In this paper, we propose a cyborg sensing platform that leverages the acute olfactory sensing capability of locusts (Schistocerca americana) for standoff detection of target chemicals. Contrary to cyborg sensing technologies that are based on implantable neural devices, the proposed platform relies on extraneous palp tracking which can be measured non-invasively for extended periods of time. In this work, locusts are conditioned (trained) to respond (move their palp) to a specific target odor and the palp movements are measured in real-time using a silver-enhanced infrared reflectance technique. The measured results correlate well with a gold-standard palp tracking method. The efficacy of our platform based on behavioral readout is demonstrated for non-invasive chemical sensing.

Prior to the demonstration, several locusts will be trained on a target odor (eg. Hexanol), according to the protocol described in the appended paper. The demonstration setup (Fig 1) consists of a trained locust (free or restrained) enclosed in a transparent enclosure, an odor delivery system and a palp tracking system. The odor delivery system contains an air pump with two outputs. One of the outputs (main line) goes directly to the locust through a filter. This tube helps in maintaining a constant flow rate over the duration of the experiment. The other output passes through an odor bottle and joins the main tube. The flow through this tube is controlled by a solenoid valve that is operated by the demonstrator. The odor bottles will contain either hexanol (target odor) or benzaldehyde (control). Entire setup occupies less than 3 feet by 2 feet and requires one power outlet for driving the pump.

Achieving targeted and efficient neural excitation is one of the major challenges in the design of implantable electroceutical devices. In this study, we explore the potential of using direct-contact ultrasound to localize and enhance the process of electrical current stimulation. The underlying premise of this study is to use ultrasonic pulses to vary the non-linear capacitive element formed by the neural membrane which would result in an ionic charge-pump that would reduce the activation threshold for a subsequent electrical stimulation. We have tested this hypothesis using a phantom experiment where a millimeter-scale ultrasonic crystal was affixed directly to the sciatic nerve of a frog and was driven both by a continuous train and by a 5 ms train of 3 MHz pulses with a monophasic electrical stimulus pulse applied at varying latencies. Compound action potential amplitudes were recorded from the gastrocnemius muscle during dual-mode stimulation, and were compared to baseline amplitudes. The experimental results showed that a downward shift in strength-duration was evident, and that a larger latency between ultrasound and electrical stimulation appeared to produce a larger amplitude with respect to the baseline, while near-simultaneous stimulation showed a suppression of action potential amplitude.

In this paper we exploit graphite's thermal absorption properties to drive the process of analyte sampling in paper-based biosensors. Graphite structures can be easily patterned or drawn on paper using a standard pencil and selective heating of the patterned layers can be remotely achieved using a light source. The resulting thermal gradient manifests itself as concentration gradients across the paper substrate which then triggers the flow of analyte to the selective areas. In this paper we have validated this hypothesis using a prototype made out of a low-cost filter paper substrate and a 300mW 808nm remote infrared laser source. Compared to a control paper substrate, we show an increase in temperature by more than 70°C (from 50°C to 120°C) in areas where the graphite is patterned. As a result the proposed prototype is also shown to demonstrate a higher sample-flow rate compared to the control. We anticipate that the proposed remote triggering of sample acquisition would be useful for different variants of paper-based biosensors that need to be integrated inside the food-package.

A major limitation in authenticating passive and remotely powered sensors, tags and cards (for e.g. radio-frequency identification tags or credit cards) is that these devices do not have access to a continuously running system clock. This obviates the use of SecureID type authentication techniques involving random keys and tokens that need to be periodically generated and synchronized. In this paper we present a dynamic hardware-software authentication approach for passive assets using zero-power timers and synchronization circuits. The timers are shown to achieve robust temporal synchronization due to the self-powering and self-compensating physics of Fowler-Nordheim (FN) quantum transport of electrons tunneling onto a floating-gate. The output of the timers are then used to seed a pseudorandom number generator which produce random and synchronized authentication tokens. We validate the proposed approach using prototypes fabricated in a standard 0.5μm CMOS process where we demonstrate synchronization accuracy greater than 40dB. Compared to conventional static authentication methods that are currently used for passive sensors, tags and cards, the proposed dynamic approach should provide enhanced security and make it more immune to counterfeiting and data theft.

In this paper we present the design and implementation of CMOS telemetry circuits that can be used for in-vivo wireless sonomicrometry. The proposed transmitter circuit uses a digital pulse modulator that directly drives a sonomicrometry crystal using a train of ultra-wide-band pulses. The receiver is also designed using a pulse modulator which is configured to measure the energy of the ultrasonic pings received by the crystal. Using measured results from a prototype fabricated in a 0.5-μm CMOS process we verify the operation of the telemetry circuits and using 1mm diameter sonomicrometry crystals we present measurement results using three types of phantom setups: (a) a saline bath; (a) a chicken bone/bone-marrow; and (b)chicken breast and tissue. The measurement results demonstrate that for the three phantoms the integrated telemetry system can be used for bi-directional data transfer at a rate of 1 Kbps with a power dissipation of 611 μW.

By incorporating sensing capabilities in passive radio-frequency identification (RFID) tagging technology it is possible to extend the coverage of Internet-of-Things (IoT) to monitor the health of different segments of a large civil infrastructure like pavement highway, buildings or a multi-span bridge. The challenge in this regard is to deliver energy to the RFID sensors that are embedded inside the structures in a manner that they can continuously sense for occurrence of any rare structural events. This paper summarizes some of the progress that has been made to-date in the area of self-powered RFID sensor networks within the concept of IoT. The core sensor uses a self-powering method which directly harvests computational and storage energy from slight strain-variations in the structure. The event signatures can then be stored on a non-volatile memory and remotely retrieved at a later period of time. In this “sense now retrieve later” paradigm, self-powering is only used for continuous sensing and data-logging of essential statistics; whereas, data retrieval and reconfiguration is achieved using a low-cost commercial RFID system. Another advantage of using a commercial RFID system for data retrieval is that the related standards and FCC compliance are well established and the technology can be easily integrated with other IoT network infrastructure.

In this paper we explore the limits of self-powering a piezoelectricity driven hot-electron injection (p-HEI) device used for monitoring mechanical activity in biomechanical implants and structures. Previously reported p-HEI devices operate by harvesting energy from a piezoelectric transducer to generate current an voltage references which are then used for initiating and controlling the process of hot-electron injection. As a result, the minimum energy required to activate the device is limited by the power requirements of the reference circuits. The p-HEI device presented in this paper operates by directly exploiting the self-limiting capability of an energy transducer when driving the process of hot-electron injection in a pMOS floating-gate transistor. As a result we show that the p-HEI device can activate itself at input power levels less than 10 nW. Using a prototype fabricated in a 0.5-μm bulk CMOS process we validate the functionality of the proposed injector and show that for a fixed input power, its dynamics is quasi-linear with respect to time. The paper also presents measurement results using a cadaver bone where the fabricated p-HEI device has been integrated with a piezoelectric transducer and is used for self-powered monitoring of mechanical activity.

This paper explores the use of continuous-time Fowler-Nordheim (FN) tunneling for implementing self-powered CMOS sensors that can be used to simultaneously measure and time-stamp occurrences of rare signal events. At the core of the proposed design is a floating-gate device where the FN based electron tunneling is induced through the thin gate-oxide and the control gate is used to couple the signal that is being measured and time-stamped. The signal then modulates the shape of the FN tunneling barrier which is captured by the tunneling rate of electrons being stored on the floating-gate. Thus the sensor continuously operates without the need for any external powering and the data from the sensor can be retrieved to reconstruct the occurrence of events offline. The proof-of-concept has been validated using prototypes fabricated in a standard 0.5-μm CMOS process and the measurement results show that less than 100 fJ of sensing energy is required for event recording and time-stamping.

Many packaging and structural materials are made of conductive materials such as metal or carbon-fiber composites, which limits the use of embedded radio frequency-based telemetry systems for sensing. In this paper, we present the design of a complete passive ultrasonic energy harvesting and back-telemetry system that exploits near-field acoustic coupling to wirelessly transfer energy and data across conductive barriers. The use of near-field operation makes the telemetry robust to multipath reflections that occur at barrier discontinuities and robust to crosstalk when multiple sensors are simultaneously interrogated. Underlying the proposed architecture is a system-on-chip (SoC) that integrates different ultrasonic energy harvesting and telemetry modules. The operation of the system has been verified using SoC prototypes fabricated in a 0.5-μm CMOS process which have been integrated with a piezoelectric transducer attached to an aerospace-grade aluminum substrate. Measured results show that the proposed near-field ultrasonic telemetry system can effectively operate across a 2-mm-thick metallic barrier at a frequency of 13.56 MHz with the SoC consuming 22.3 μW of power.

While radio-frequency based remote powering and back-telemetry is popular for many of the surface implants, like neural prosthesis or under-the-skin implanted batteries, it is not suitable for implants located deep inside the tissue. In this paper, we investigate the feasibility of using a commercial off-the-shelf (COTS), diagnostic ultrasound technology for delivering energy to a sub-cm2sized device implanted at depths more than 10cm away from the tissue surface. Using a COTS 3.5MHz ultrasound scanner we show how the B-mode interrogation protocol can be used to deliver energy to an encapsulated PZT transducer and how the B-mode video sequence can be parsed to retrieve the data from the transducer. In this paper we also discuss the limits of energy transfer at different implantation depths and we also discuss the energy requirements at the implant to achieve robust data transfer.

In this paper, we show that a silver-enhancement technique can be used to self-assemble a radio-frequency (RF) antenna which then can be used for designing a radio-frequency identification (RFID) based biosensor. Using the proposed biosensor, the concentration of target analytes or pathogens can be remotely interrogated in a concealed, packaged or in a bio-hazardous environment, where direct measurement is considered to be impractical. The presence of the target analytes or pathogens, self-powers a silver-enhancement process which then assembles a chain of micro-monopole antennas. As the size of the silver-enhanced particles grows, the chain of micro-antenna segments bridge together to complete a dipole structure that reflects impinging RF signals at a desired frequency. We validate the proof-of-concept for IgG detection and demonstrate that different concentrations of rabbit IgG (ranging from 20ng to 60ng in this paper) can be detected based on the strength of the reflected RF signal received at a 915MHz COTS RFID reader.

Floating-gate (FG) transistors are commonly used in synthetic neural systems for implementing analog multipliers. However, conventional floating-gate multipliers are sensitive to variations in temperature which limit their application to only controlled environments. Previously, we had reported an off-chip temperature compensation algorithm for floating-gate current memories which used varactors to cancel out the temperature dependent factors. In this paper, we report a continuous-time circuit implementation of the temperature compensation algorithm and show that it enables on-chip implementation of temperature compensated current amplifiers and analog multipliers. Using measured results from fabricated prototypes in a 0.5μm CMOS process, we demonstrate the functionality of the compensation circuit and show that it leads to an order-of-magnitude lower temperature sensitivity for FG multipliers when compared to an uncompensated case.

Measuring head impacts in helmeted sports is important for prognosticating onset of mild traumatic brain injuries (MTBIs) or concussions. In this paper we present a miniature battery-less, self-powered sensor that can be embedded inside sport helmets and can continuously monitor and log the statistics of different levels of helmet impacts. At the core of the proposed sensor is a novel time-dilation circuit which allows measurement of the high-levels of impact energy. An array of linear floatinggate injector is used for storing the location of the sensor on the helmet and for logging the statistics of helmet impacts which can be retrieved using an external plug-and-play reader. Measured results from prototypes fabricated in a 0.5 μm CMOS process validate the functionality of the sensor when subjected to controlled drop tests.

Bias-scalability in analog CMOS circuits refers to a current-mode design paradigm where the operation of the circuit remains invariant to the operating conditions (weak-inversion, moderate-inversion or strong-inversion) of the transistors. In this paper we present the design and implementation of a bias-scalable analog support vector machine (SVM) based on our previously reported margin propagation (MP) technique. All the computation in the proposed SVM occur in the logarithmic domain and requires only the use of addition, subtraction and threshold operation which can be implemented using KCL and diodes. The SVM parameters are stored on an array of temperature compensated floating-gate current memories and the training of the SVM is achieved using an offline procedure. Measured results from a SVM prototyped in a 0.5μm CMOS process validates the bias-scalability across different MOSFET operating regimes.

Physical processes like changes in ambient temperature, pressure, material accumulation or growth induce stress/strain responses in structures (civil or biomechanical) that occur at frequencies ranging from Hz down to micro-Hertz (μHz). The quasi-static nature of this process poses a challenge for designing self-powered sensors that not only monitor these physical processes but at the same time scavenge operational energy for sensing, computation and storage from the signal being monitored. In this paper we propose a novel sub-Hz self-powered sensing approach which exploits the combination of the physics of post-buckling response in slender elastic columns and the physics of hot-electron injection in floating-gate transistors. Experimental results using a fabricated prototype demonstrate that the sensor can self-power, compute and record the statistics of quasi-static input signals operating at frequencies down to 1mHz.

While floating-gate transistors are attractive as a compact non-volatile storage of analog and neural network parameters, precise and fast adaptation of the stored parameters through digital command and control is a challenge. In this paper we present the design of a high-density array of analog floating-gate memory that can be precisely and independently updated using digital timing interrupts. At the core of the proposed array is our previously reported negative-feedback architecture that allows linearizing of the impact ionized hot-electron injection (IHEI) process and the Fowler-Nordheim (FN) tunneling process in FG transistors. Using a capacitive switching approach, FN tunneling can be independently applied to each of memory cell of the proposed array without affecting the stored values in the other cells. As a result, bi-directional digital updates with accuracy greater than 500μV can be achieved with a linearity of more than 60dB. We have validated the functionality of the analog array using a prototype fabricated in a 0.5μm CMOS process.

Linear self-powering using a piezoelectric transducer is not well suited for detecting high-velocity mechanical impacts where the level of strain inside the structure could vary by orders of magnitude. In this paper we present a novel compressive self-powering technique that uses a non-linear impedance circuit to dynamically load the output of a piezoelectric transducer and in the process reduce the magnitude of the output voltage at large levels of mechanical strain. Measured results obtained from prototypes fabricated in a 0.5-μm standard CMOS process validate the proposed compressive powering technique.

One of the major challenges in remotely powered sensors is that events being monitored can not be time-stamped due to the unavailability of a continuously active timer or system clock. Implementing such a timer would require access to a perennial source of energy, which for a structural health monitoring (SHM) application, could easily span several years. In this paper, we present a novel approach to implement self-powered timers that only requires presence of ambient thermal energy. The operational principle of the timer is based on the physics of trap-assisted electron transportation in floating-gate capacitors which yields leakage currents down to 10-21A. Using a differential architecture the proposed timer compensates for the effects of temperature variations during the timer read-out. In this paper we validate the proof-of-concept using measurement results obtained from different timer topologies which have been prototyped in a 0.5μm CMOS process.

Analog circuits that are calibrated using digital-to-analog converters (DACs) use a digital signal processor-based algorithm for real-time adaptation and programming of system parameters. In this paper, we first show that this conventional framework for adaptation yields suboptimal calibration properties because of artifacts introduced by quantization noise. We then propose a novel online stochastic optimization algorithm called noise-shaping or ΣΔ gradient descent, which can shape the quantization noise out of the frequency regions spanning the parameter adaptation trajectories. As a result, the proposed algorithms demonstrate superior parameter search properties compared to floating-point gradient methods and better convergence properties than conventional quantized gradient-methods. In the second part of this paper, we apply the ΣΔ gradient descent algorithm to two examples of real-time digital calibration: 1) balancing and tracking of bias currents, and 2) frequency calibration of a band-pass Gm-C biquad filter biased in weak inversion. For each of these examples, the circuits have been prototyped in a 0.5-μm complementary metal-oxide-semiconductor process, and we demonstrate that the proposed algorithm is able to find the optimal solution even in the presence of spurious local minima, which are introduced by the nonlinear and non-monotonic response of calibration DACs.

Floating-gate transistors serve as an attractive media for non-volatile storage of analog parameters in neural systems. However, conventional current memories based on floating-gate transistors are sensitive to variations in temperature, therefore limiting their applications to only controlled environments. In this paper we propose a temperature compensated floating-gate array that can be programmed to store currents down to picoampere level. At the core of the proposed architecture is a control algorithm that uses a varactor to adapt the floating-gate capacitance such that the temperature dependent factors can be effectively canceled. As a result, the stored current is theoretically a function of a reference current and the differential charge stored on the floating-gates. We validate the proof-of-concept using measurement results obtained from prototype current memory cells fabricated in a 0.5μm CMOS process.

In this paper we describe a self-powered micro-sensor that can be used for embedded measurement of static-strain. At the core of the proposed design is a linear floating-gate injector that can achieve more than 13 bits of precision in sensing, signal integration and non-volatile storage. The injectors are self-powered by piezoelectric transducers which convert mechanical energy due to strain-variations into electrical energy. A differential injector topology is then used to measure static-strain by integrating the difference between the signal energy generated during the positive and negative strain-cycles. We demonstrate the proof-of-concept using measurement results obtained from prototypes fabricated in a 0.5-µm standard CMOS process.

Analog circuits that use on-chip digital-to-analog converters for calibration use a DSP based algorithm for adapting and calibrating the system parameters. In this paper, we show that this conventional method suffers from artifacts due to quantization noise which adversely affects the real-time and precise convergence to the desired parameters. We propose a ΣΔ based gradient-descent learning that can noise-shape the quantization noise during the adaptation procedure and in the process achieve faster convergence compared to the conventional quantized gradient-descent approach. We also show that when the analog circuits suffer from non-linearities and non-monotonic response of the calibration DACs, the proposed algorithm is still able to find the optimal system solution without getting trapped into local minima. Using measured results obtained from prototype fabricated in a 0.5-μm CMOS process, we demonstrate the robustness of the proposed algorithm for the task of: (a) compensating and tracking of offset parameters; and (b) calibration of the center frequency of a sub-threshold gm-C biquad filter.

In this paper, we present a novel speech feature extraction algorithm based on a hierarchical combination of auditory similarity and pooling functions. The computationally efficient features known as “Sparse Auditory Reproducing Kernel” (SPARK) coefficients are extracted under the hypothesis that the noise-robust information in speech signal is embedded in a reproducing kernel Hilbert space (RKHS) spanned by overcomplete, nonlinear, and time-shifted gammatone basis functions. The feature extraction algorithm first involves computing kernel based similarity between the speech signal and the time-shifted gammatone functions, followed by feature pruning using a simple pooling technique (“MAX” operation). In this paper, we describe the effect of different hyper-parameters and kernel functions on the performance of a SPARK based speech recognizer. Experimental results based on the standard AURORA2 dataset demonstrate that the SPARK based speech recognizer delivers consistent improvements in word-accuracy when compared with a baseline speech recognizer trained using the standard ETSI STQ WI008 DSR features.

In this paper we present a novel speech feature extraction algorithm based on sparse auditory coding and regression techniques in a reproducing kernel Hilbert space (RKHS). The features known as sparse kernel cepstral coefficients (SKCC) are extracted under the hypothesis that the noise-robust information in speech signal is embedded in a subspace spanned by overcomplete, regularized and normalized gamma- tone basis functions. After identifying the information bearing subspace, noise-robustness is achieved by sparsifying the SKCC features using simple thresholding. We show that computing the SKCC features involves correlating the speech signal with a pre-computed matrix, thus making the algorithm amenable to DSP based implementation. Speech recognition experiments using AURORA 2 dataset demonstrate that the SKCC features delivers consistent improvements in recognition performance over the state-of-the-art features under different noisy recording conditions.

One of the key factors underlying the popularity of low-density parity-check (LDPC) codes is its iterative decoding algorithm which is amenable to efficient analog and digital implementation. However, different applications of LDPC codes (e.g. wireless sensor networks) impose different sets of constraints which include speed, bit error rates (BER) and energy efficiency. Our previous work reported an algorithmic framework for designing margin propagation (MP) based LDPC decoders where the BER performance can be traded off with its energy efficiency. In this paper we present an analog current-mode implementation of an MP-based (32,8) LDPC decoder. The implementation uses only addition, subtraction and threshold operations and hence is independent of transistor biasing and robust to variations in environmental conditions (e.g. temperature). Measured results from prototypes fabricated in a 0.5 μm CMOS process verify the functionality of a (32,8) LDPC decoder and demonstrate superior BER performance compared to the state-of-the-art analog min- sum decoder at SNR greater than 3.5 dB.

We had previously reported a self-powered floating- gate level-crossing sensor/processor where the energy for sensing, computation and storage was extracted directly from the input strain variations. However, self-powering was found insufficient for wireless interrogation and configuration of the sensor. In this paper, we present a hybrid energy scavenging sensor where self-powering is employed for long-term ambient mechanical strain monitoring, whereas data digitization, framing, telemetry and high-voltage floating-gate configuration/programming are performed remotely using RF powering. As a hybrid energy scavenger, the sensor can seamlessly harvest working energy from both vibrations and RF signals under different working conditions. Therefore, the sensor does not experience any down- time and can continuously operate by recording key statistics of the ambient strain signals. Sensor prototypes with an integrated 13.56MHz RF interface have been fabricated in a 0.5-μm standard CMOS process and the measured results verify the long-term autonomous monitoring capability of the sensor.

Limit-cycle dynamics embedded in neuronal spike-trains can form robust representations for encoding auditory spectral features. In this paper, we present speaker identification experiments based on limit-cycle statistics that were computed using spike-trains obtained from a spike-based silicon cochlea. The features included in this study were: (a) spike-rate; (b) inter-spike-interval distribution; and (c) inter-spike-velocity features, which were then used to design a speaker identification system based on a Gini-support vector machine (SVM) classifier. The results show a strong correlation between the information contained in the spike-rate/interval features and the spike-velocity/acceleration features indicating redundant encoding of auditory features which could be important for achieving noise-robustness in real-world recording conditions.

The performance of acoustic source separation algorithms significantly degrades when they applied to signals recorded using miniature microphone arrays where the distances between the microphone elements are much smaller than the wavelength of acoustic signals. This can be attributed to limited dynamic range (determined by analog-to-digital conversion) of the sensor which is insufficient to overcome the artifacts due to large cross-channel redundancy, non-homogeneous mixing and high-dimensionality of the signal space. This paper presents some of the recent progress in the area of sigma-delta learning which integrates statistical learning with analog-to-digital process and enables super-resolution auditory localization and separation. Experiments with synthetic and real recordings demonstrate significant and consistent performance improvements when the proposed approach is used as the analog-to-digital front-end to conventional source separation algorithms.

Inverse problems in nano-biomolecular circuits typically involve stochastic functional elements that admit non-linear relationships between different circuit variables. In this regard, a factor graph representation serves as an important visualization and analysis tool that can be used to compute inferences over an arbitrary large-scale biomolecular circuit. Solving the inverse problem using a factor graph entails passing of messages/signals between the internal nodes of the biomolecular circuit, and the steady-state distribution of the messages can be used to determine the dynamics of the circuit and the final solution. In this paper, we present an open-source simulation tool that we have developed which can be used to verify the functionality of a generic nano-biomolecular circuit. As a representative example, we apply the simulation software to estimate the reliability of a 103size biosensor array where each element of the array is comprised of our previously reported antigen-antibody based biomolecular circuit. This example will demonstrate the utility of the proposed software in emulating the functionality of micro and nano biosensor arrays without resorting to time-consuming and laborious fabrication procedure and laboratory experiments.

Floating-gate transistors have been extensively used as analog memory elements in adaptive learning and neural systems. However, conventional techniques for storing and programming sub-threshold currents on floating-gate transistors are sensitive to temperature variations thus limiting their applicability to controlled environments. In this paper, we propose a temperature compensated floating-gate array which can be used to store and program currents down to nanoampere level. The core of the proposed current memory is a dual-channel floating-gate transistor based current reference circuit which uses a linear resistor in translinear loop. As a result the stored current is linearly proportional to the charge on the floating-gate and hence can be precisely programmed. The paper presents results from a prototype fabricated in a 0.5-μm CMOS process which validates the functionality of the proposed current memory cell.

One of the key factors underlying the popularity of Low-density parity-check (LDPC) code is its iterative decoding algorithm that is amenable to efficient hardware implementation. Even though different variants of LDPC iterative decoding algorithms have been studied for its error-correcting properties, an analytical basis for evaluating energy efficiency of LDPC decoders has not been reported. In this paper, we present a framework of a parameterized LDPC decoding algorithm that can be optimized to produce sparse representation of communication messages used in iterative decoding. The sparsity of messages is determined by its differential entropy and has been used as a theoretical metric for determining the energy efficiency of an iterative LDPC decoder. At the core of the proposed algorithm is margin propagation (MP) which approximates the log-sum-exp function used in conventional sum-product (SP) decoders by a piecewise linear (PWL) function. Using Monte-Carlo simulations, we demonstrate that the MP decoding leads to a significant reduction in message entropy compared to a conventional SP decoder, while incurring a negligible performance penalty (less than 0.03 dB). The proposed work therefore lays the foundation for design of parameterized LDPC decoders whose bit-error-rate performance can be effectively traded-off with respect to different energy efficiency constraints as required by different set of applications.

For many recognition systems, the feature extraction unit forms the most computationally intensive and power consuming component. In this paper, we present a design of an analog-to-information converter that directly produces a pulse-encoded representation of linear predictive coded (LPC) features corresponding to an input analog signal. At the core of proposed design is a sigma-delta modulation procedure that is embedded within a learning step. Measured results from a fabricated prototype in a 0.5 mum CMOS technology demonstrate the real-time functionality of the learner in extracting 6-dimensional online LPC features from input speech signal while consuming only 450 muW.

Many signals of interest in structural engineering, for example seismic activity, lie in the infrasonic range (frequency less than 20 Hz). This poses a significant challenge for developing batteryless sensors that are required not only to monitor rare infrasonic events but also to harvest the energy for sensing, computation and storage from the signal being monitored. In this paper, we show that a linear injection response of our previously reported piezo-floating-gate sensor is ideal for self-powered sensing and computation of infrasonic signals. Our experimental results demonstrate that the sensor fabricated in a 0.5 mum CMOS technology can compute and record level crossing statistics of an input seismic event. Collected data are in good agreement with results obtained using a standard data acquisition system. Also, the sensor consumes less than 100 nA of current, which makes its operation based on infrasonic power-harvesting feasible.

This paper presents a 128 times 128 charge-mode CMOS imaging sensor that computes separable transforms directly on the focal plane. The pixel is a unique extension of the widely reported active pixel sensor (APS) cell. By capacitively coupling across an array of such cells onto switched capacitor circuits, computation of any unitary 2-D transform that is separable into inner and outer products is possible. This includes the Walsh, Hadamard and Haar basis functions. This scheme offers several advantages including multiresolution imaging, inherent de-noising, compressive sampling and lower integration voltage and faster readout. The chip was implemented on a 0.5 mum CMOS process and measures 9 mm2in MOSIS' submicron design rules.

In this paper, we present a non-linear filtering approach for extracting noise-robust speech features that can be used in a speaker verification task. At the core of the proposed approach is a time-series regression using reproducing kernel Hilbert space (RKHS) based methods that extracts discriminatory non-linear signatures while filtering out the non-informative noise components. A linear projection is then used to map the characteristics of the RKHS regression function into a linear-predictive vector which is then presented as an input to a back-end speaker verification engine. Experiments using the YOHO speaker verification corpus demonstrate that a recognition system trained using the proposed features demonstrate consistent improvements over an equivalent Mel-frequency cepstral coefficients (MFCCs) based verification system for signal-to-noise levels ranging from 0-30 dB.

This paper presents a dual-channel architecture for floating-gate transistors that can alleviate the detrimental effects of oxide-traps seen in indirect programming techniques. The proposed transistor consists of four input/output ports that allow multiple paths for drain currents to flow and yet share the same gate-oxide and poly-silicon gate. As a result, one pair of the ports can be used for indirect programming, whereas the other pair can be actively connected to other analog circuits. Compared with the existing approaches for floating-gate programming, the proposed technique avoids disruption of the circuit operation and eliminates the effect of oxide-traps as well. In this paper we present measured results obtained from a dual-channel floating-gate current reference which has been fabricated in a 0.5-µm standard CMOS process.

Silver-enhanced labeling method that is employed in immunochromatographic assay provides an effective way of improving the sensitivity of detecting pathogens. In this paper, we apply the silver enhancement approach for providing signal amplification in conductimetric biochips which employ gold nanoparticles to bridge on a high-density microelectrode array for detecting gold nanoparticles. One of the measurement methods presented in this paper is the silver enhancing time that is shown to be an indicator of the concentration of gold nanoparticles. The method provides an alternative to existing detection methods and it is straightforward to achieve high-sensitivity in detection. The measured results presented in this paper are based on a high-density interdigital microelectrodes with a 4 mum gap where we show detection limits as low as 25 femtomolar.

Many source separation algorithms fail to deliver robust performance when applied to signals recorded using high-density microphone arrays where distance between sensor elements is much smaller than the wavelength of the signal of interest. This can be attributed to limited dynamic range (determined by analog-to-digital conversion) of the sensor which is insufficient to overcome the artifacts due to cross-channel redundancy, non-homogenous mixing and high-dimensionality of the signal space. In this paper we propose a novel framework that overcomes these limitations by integrating learning algorithms directly with analog-to- digital conversion. At the core of the proposed approach is a novel regularized min-max optimization approach that yields "delta-sigma" limit-cycles. An on-line adaptation modulates the limit-cycles to enhance resolution in the signal sub-spaces containing non-redundant information. Numerical experiments simulating far-field recording conditions demonstrate consistent improvements over a benchmark setup used for independent component analysis (ICA).

Many source separation algorithms fail to deliver robust performance in presence of artifacts introduced by cross-channel redundancy, non-homogeneous mixing and high- dimensionality of the input signal space. In this paper, we propose a novel framework that overcomes these limitations by integrating learning algorithms directly with the process of signal acquisition and sampling. At the core of the proposed approach is a novel regularized max-min optimization approach that yields "sigma-delta" limit-cycles. An on-line adaptation modulates the limit-cycles to enhance resolution in the signal sub- spaces containing non-redundant information. Numerical experiments simulating near-singular and non-homogeneous recording conditions demonstrate consistent improvements of the proposed algorithm over a benchmark when applied for independent component analysis (ICA).

Measurement of cumulative loading statistics experienced by a structure is essential for monitoring long-term fatigue in biomechanical implants. However, the total power that can be harvested using typical in-vivo strain levels is less than 1 muW. In this paper we characterize the performance of a silicon floating-gate injector array that can be used in conjunction with a piezoelectric transducer to facilitate long- term, battery-less fatigue monitoring. Measured results from a fabricated prototype in a 0.5 mum CMOS process demonstrate that device can sense, compute and store loading statistics for over 70,000 of continuous simulated stress-strain cycles and this value can be increased beyond 107by appropriate scaling of the system parameters. The measured results also show excellent agreement with its theoretical model and the nominal power dissipation of the array was measured to be less than 800 nW.

Factors that affect the accuracy of the biosensor systems range from errors in device fabrication to stochastic interaction between biomolecules. In this paper we present a framework for designing and evaluating biosensor encoding and decoding algorithms based on forward error-correcting (FEC) principles, which can improve the accuracy of pathogen detection. The model biosensor used in this paper is an immunosensor that uses computational primitives inherent in antigen-antibody interaction to achieve a transistor like operation. Fundamental logic gates have been embedded into an equivalent low-density parity check (LDPC) biosensor encoder and a corresponding sum- product decoding algorithm is presented for error correction. The performance of the encoding-decoding algorithm has been verified using behavioral simulations demonstrating its utility for designing reliable biosensors. The simulation study also reveals a novel co-detection principle that can be a promising method for significantly enhancing the pathogen detection limit.

In this paper we describe the fabrication and characterization of a multiplexed biosensor based on molecular bio-wires that can be used for detecting multiple pathogens in a biological sample. At the core of the proposed device is a biosensor that operates by converting binding events between antigen and antibody into a measurable electrical signal using polyaniline nanowires as transducers. By mixing and patterning antibodies at different spatial locations of the biosensor, the response of the biosensor can be configured to detect the presence of either one of several pathogens present in the analyte, thus making it ideal for rapid environment screening applications. Experiments using the biosensor array specific to B. cereus and E. coli bacteria validate the functionality of the proposed multiplexed architecture.

This paper presents a novel approach for designing energy-scalable analog VLSI recognizers. Unlike conventional designs that rely on the translinear response of MOS transistors biased in weak inversion, the proposed approach uses margin propagation, enabling system operation independent of MOS transistor biasing conditions. In this paper margin propagation has been used for designing energy-scalable support vector machines (SVM) whose power and speed requirements can be configured dynamically without any degradation in performance. A prototype SVM operating with 14 dimensional feature vectors and 28 support vectors has been designed and fabricated in a0.5μmCMOS process. The chip integrates an array of floating gate transistors that serve as storage for SVM parameters. Circuit level simulations demonstrate near identical performance to an equivalent software-based SVM with power dissipation less than1μW at a rate of 100 classifications per second.

In this paper we describe an implementation and modeling of a novel fatigue monitoring sensor based on integration of piezoelectric transduction with floating gate avalanche injection. The miniaturized sensor enables continuous battery-less monitoring and failure predictions of biomechanical implants. Measured results from a fabricated prototype in a 0.5μm CMOS process demonstrate excellent agreement with the theoretical model in computing cumulative statistics of electrical signals generated by the piezoelectric transducer. The power dissipation of the sensor is less than 1μW which makes it attractive for integration with biocompatible poly-vinylidene diflouride (PVDF) based transducers.

The performance of speech recognition systems depends on consistent quality of the speech features across variable environmental conditions encountered during training and evaluation. This paper presents a kernel-based nonlinear predictive coding procedure that yields speech features which are robust to nonstationary noise contaminating the speech signal. Features maximally insensitive to additive noise are obtained by growth transformation of regression functions that span a reproducing kernel Hilbert space (RKHS). The features are normalized by construction and extract information pertaining to higher-order statistical correlations in the speech signal. Experiments with the TI-DIGIT database demonstrate consistent robustness to noise of varying statistics, yielding significant improvements in digit recognition accuracy over identical models trained using Mel-scale cepstral features and evaluated at noise levels between 0 and 30-dB signal-to-noise ratio.

Analog iterative decoders offer several advantages over their digital counterparts in terms of speed and power consumption. The current state of art CMOS analog decoders uses MOS transistors biased in weak inversion which limits their speed of operation. In this paper a novel analog decoding network is presented which can operate with MOS transistor biased both in weak and strong inversion. The principle of operation is based on margin propagation algorithm which requires only addition, subtraction and thresholding operation which can be easily implemented in analog VLSI. A current mode implementation of the decoder is proposed which operates directly in log-likelihood space. This not only improves the speed of convergence for iterative decoding but also enhances the dynamic range of the decoder. Simulation based on a simple tail-biting trellis is presented that demonstrate the decoding characteristic and speed of operation of the proposed margin propagation network

This paper presents an alternative to a logarithmic response CMOS imager that utilizes an in-pixel, time-based compressive map for capturing scenes with wide dynamic range. The imager employs a correlated double sampling technique that significantly reduces the effects of parasitic capacitance and mismatch in active-pixel circuits. An on-line adaptation technique that adjusts the parameter of the compressive map compensates for variable illumination conditions across different scenes, achieving large dynamic range. The proposed pixel architecture and algorithm have been implemented with relatively few transistors and with a fill factor of 17%. An imager consisting of an array of 110 times 80 pixels has been designed and fabricated using a 0.5mum CMOS process. Simulation and preliminary testing results demonstrate the functionality of the imager to adapt its response under different illumination conditions

A key challenge in designing analog-to-digital converters for cortically implanted prosthesis is to sense and process high-dimensional neural signals recorded by the micro-electrode arrays. In this paper, we describe a novel architecture for analog-to-digital (A/D) conversion that combines conversion with spatial de-correlation within a single module. The architecture called multiple-input multiple-output (MIMO) is based on a min-max gradient descent optimization of a regularized linear cost function that naturally lends to an A/D formulation. Using an online formulation, the architecture can adapt to slow variations in cross-channel correlations, observed due to relative motion of the microelectrodes with respect to the signal sources. Experimental results with real recorded multi-channel neural data demonstrate the effectiveness of the proposed algorithm in alleviating cross-channel redundancy across electrodes and performing data-compression directly at the A/D converter.

A robust speech feature extraction procedure, by kernel regression nonlinear predictive coding, is presented. Features maximally insensitive to additive noise are obtained by growth transformation of regression functions spanning a reproducing kernel Hilbert space (RKHS). Experiments on TI-DIGIT demonstrate consistent robustness of the new features to noise of varying statistics, yielding significant improvements in digit recognition accuracy over identical models trained using Mel-scale cepstral features and evaluated at noise levels between 0 and 30 dB SNR.

An auditory perception model for noise-robust speech feature extraction is presented. The model assumes continuous-time filtering and rectification, amenable to real-time, low-power analog VLSI implementation. A 3 mm/spl times/3 mm CMOS chip in 0.5 /spl mu/m CMOS technology implements the general form of the model with digitally programmable filter parameters. Experiments on the TI-DIGIT database demonstrate consistent robustness of the new features to noise of various statistics, yielding significant improvements in digit recognition accuracy over models identically trained using Mel-scale frequency cepstral coefficient (MFCC) features.

An analog system-on-chip for kernel-based pattern classification and se- quence estimation is presented. State transition probabilities conditioned on input data are generated by an integrated support vector machine. Dot product based kernels and support vector coefficients are implemented in analog programmable floating gate translinear circuits, and probabil- ities are propagated and normalized using sub-threshold current-mode circuits. A 14-input, 24-state, and 720-support vector forward decod- ing kernel machine is integrated on a 3mm3mm chip in 0.5m CMOS technology. Experiments with the processor trained for speaker verifica- tion and phoneme sequence estimation demonstrate real-time recognition accuracy at par with floating-point software, at sub-microwatt power. 1 Introduction The key to attaining autonomy in wireless sensory systems is to embed pattern recognition intelligence directly at the sensor interface. Severe power constraints in wireless integrated systems incur design optimization across device, circuit, architecture and system levels [1]. Although system-on-chip methodologies have been primarily digital, analog integrated sys- tems are emerging as promising alternatives with higher energy efficiency and integration density, exploiting the analog sensory interface and computational primitives inherent in device physics [2]. Analog VLSI has been chosen, for instance, to implement Viterbi [3] and HMM-based [4] sequence decoding in communications and speech processing. Forward-Decoding Kernel Machines (FDKM) [5] provide an adaptive framework for gen- eral maximum a posteriori (MAP) sequence decoding, that avoid the need for backward recursion over the data in Viterbi and HMM-based sequence decoding [6]. At the core of FDKM is a support vector machine (SVM) [7] for large-margin trainable pattern classifi- cation, performing noise-robust regression of transition probabilities in forward sequence estimation. The achievable limits of FDKM power-consumption are determined by the number of support vectors (i.e., regression templates), which in turn are determined by the complexity of the discrimination task and the signal-to-noise ratio of the sensor inter- face [8]. MVM MVM 24 2 1 SUPPORT VECTORS KERNEL s x s i1 30x24 30x24 K(x,x s ) x f (x) 14 24x24 i1 INPUT NORMALIZATION P P i1 i24 24x24 24 FORWARD DECODING j[n-1] 24 i[n] Figure 1: FDKM system architecture. In this paper we describe an implementation of FDKM in silicon, for use in adaptive se- quence detection and pattern recognition. The chip is fully configurable with parameters directly downloadable onto an array of floating-gate CMOS computational memory cells. By means of calibration and chip-in-loop training, the effect of mismatch and non-linearity in the analog implementation is significantly reduced. Section 2 reviews FDKM formulation and notations. Section 3 describes the schematic details of hardware implementation of FDKM. Section 4 presents results from experiments conducted with the fabricated chip and Section 5 concludes with future directions. 2 FDKM Sequence Decoding FDKM recognition and sequence decoding are formulated in the framework of MAP (max- imum a posteriori) estimation, combining Markovian dynamics with kernel machines. The MAP forward decoder receives the sequence X[n] = {x[1], x[2], . . . , x[n]} and pro- duces an estimate of conditional probability measure of state variables q[n] over all classes i 1, .., S, i[n] = P (q[n] = i | X[n]). Unlike hidden Markov models, the states directly encode the symbols, and the observations x modulate transition probabilities be- tween states [6]. Estimates of the posterior probability i[n] are obtained from estimates of local transition probabilities using the forward-decoding procedure [6] S P i[n] = ij [n] j [n - 1] (1) j=1 where Pij[n] = P (q[n] = i | q[n - 1] = j, x[n]) denotes the probability of making a transition from class j at time n - 1 to class i at time n, given the current observation vector x[n]. Forward decoding (1) expresses first order Markovian sequential dependence of state probabilities conditioned on the data. The transition probabilities Pij[n] in (1) attached to each outgoing state j are obtained by normalizing the SVM regression outputs fij(x): Pij[n] = [fij(x[n]) - zj[n]]+ (2) Vdd M4 A V V g ref g V M1 V M2 c c M3 C B V V I tunn tunn out Iin (a) (x.x )2 Vdd s x M7 M9 M10 M8 Vbias M5 M6 (b) sK(x, x ) ij s Figure 2: Schematic of the SVM stage. (a) Multiply accumulate cell and reference cell for the MVM blocks in Figure 1. (b) Combined input, kernel and MVM modules. where [.]+ = max(., 0). The normalization mechanism is subtractive rather than divisive, with normalization offset factor zj[n] obtained using a reverse-waterfilling criterion with respect to a probability margin [10], [fij(x[n]) - zj[n]]+ = . (3) i Besides improved robustness [8], the advantage of the subtractive normalization (3) is its amenability to current mode implementation as opposed to logistic normalization [11] which requires exponentiation of currents. The SVM outputs (margin variables) fij(x) are given by: N f s K ij (x) = (x, x ij s) + bij (4) s where K(, ) denotes a symmetric positive-definite kernel1 satisfying the Mercer condi- tion, such as a Gaussian radial basis function or a polynomial spline [7], and xs[m], m = 1, .., N denote the support vectors. The parameters s in (4) and the support vectors x ij s[m] are determined by training on a labeled training set using a recursive FDKM procedure de- scribed in [5]. 3 Hardware Implementation A second order polynomial kernel K(x, y) = (x.y)2 was chosen for convenience of im- plementation. This inner-product based architecture directly maps onto an analog compu- tational array, where storage and computation share common circuit elements. The FDKM 1K(x, y) = (x).(y). The map () need not be computed explicitly, as it only appears in inner-product form. f [n] Vdd Vdd Vdd Vdd ij i[n] M6 M9 Aij P [n] ij M7 M8 M4 M2 M3 M5 M1 Vref j[n-1] Figure 3: Schematic of the margin propagation block. system architecture is shown in Figure 1. It consists of several SVM stages that generates state transition probabilities Pij[n] modulated by input data x[n], and a forward decoding block that performs maximum a posteriori (MAP) estimation of the state sequence i[n].

A robust and accurate image recognizer for cephalometric landmarking is presented. The recognizer uses Gini support vector machine (SVM) to model discrimination boundaries between different landmarks and also between the background frames. Large margin classification with non-linear kernels allows to extract relevant details from the landmarks, approaching human expert levels of recognition. In conjunction with projected principal-edge distribution (PPED) representation as feature vectors, GiniSVM is able to demonstrate more than 95% accuracy for landmark detection on medical cephalograms within a reasonable location tolerance value.

A robust and accurate image recognizer for cephalometric landmarking is presented. The recognizer uses Gini support vector machine (SVM) to model discrimination boundaries between different landmarks and also between the background frames. Large margin classification with non-linear kernels allows to extract relevant details from the landmarks, approaching human expert levels of recognition. In conjunction with projected principal-edge distribution (PPED) representation as feature vectors, GiniSVM. is able to demonstrate more than 95% accuracy for landmark detection on medical cephalograms within a reasonable location tolerance value.

Training of support vector machines (SVMs) amounts to solving a quadratic programming problem over the training data. We present a simple on-line SVM training algorithm of complexity approximately linear in the number of training vectors, and linear in the number of support vectors. The algorithm implements an on-line variant of sequential minimum optimization (SMO) that avoids the need for adjusting select pairs of training coefficients by adjusting the bias term along with the coefficient of the currently presented training vector. The coefficient assignment is a function of the margin returned by the SVM classifier prior to assignment, subject to inequality constraints. The training scheme lends efficiently to dedicated SVM hardware for real-time pattern recognition, implemented using resources already provided for run-time operation. Performance gains are illustrated using the Kerneltron, a massively parallel mixed-signal VLSI processor for kernel-based real-time video recognition.

A forward decoding approach to kernel machine learning is presented. The method combines concepts from Markovian dynamics, large margin classifiers and reproducing kernels for robust sequence detection by learning inter-data dependencies. A MAP (maximum a posteriori) sequence estimator is obtained by regressing transition probabilities between symbols as a function of received data. The training procedure involves maximizing a lower bound of a regularized cross-entropy on the posterior probabilities, which simplifies into direct estimation of transition probabilities using kernel logistic regression. Applied to channel equalization, forward decoding kernel machines outperform support vector machines and other techniques by about 5dB in SNR for given BER, within 1 dB of theoretical limits.

Forward decoding kernel machines (FDKM) combine large-margin clas(cid:173) sifiers with hidden Markov models (HMM) for maximum a posteriori (MAP) adaptive sequence estimation. State transitions in the sequence are conditioned on observed data using a kernel-based probability model trained with a recursive scheme that deals effectively with noisy and par(cid:173) tially labeled data. Training over very large data sets is accomplished us(cid:173) ing a sparse probabilistic support vector machine (SVM) model based on quadratic entropy, and an on-line stochastic steepest descent algorithm. For speaker-independent continuous phone recognition, FDKM trained over 177 ,080 samples of the TlMIT database achieves 80.6% recognition accuracy over the full test set, without use of a prior phonetic language model.