A fast heuristic method for the scheduling problem that minimizes hardware costs of functional units, registers, and buses on the basis of an integer linear programming (ILP) model is proposed. In the method, the total computation time can be greatly reduced compared to the general ILP method, since the number of the integer variables which appear in the ILP formulation is reduced by introducing a stepwise expansion approach. Results obtained for a practical scheduling problem indicate that the computation time of the proposed method is linear to the number of the control steps, and optimal or near-optimal solutions can be found.>

The authors propose a new layout method based on a block compaction and two-adjacent-side channel router for building block VLSI. In this method, the block compaction and global routing are carried out simultaneously and by introducing a new channel router it is possible to avoid unnecessary detour of the wires and reduce the dead space. The present channel routing approach has a remarkable feature that its routability is 100%. Experimental results are shown to compare this method with the previous method.>

A one-dimensional gate assignment algorithm based on hierarchical contraction of nets is proposed. In this algorithm, a special feature of multiterminal nets plays an important role, namely that if the gates can be arranged such that the nets with fewer terminals are shorter, the chip area will be much reduced. The algorithm consists of two phases, hierarchical contraction of nets and partial gate assignment. In the first phase, the original problem is partitioned to multiple levels with the basis on contraction of multiterminal nets, and in the next phase, the gates at each level are placed close to one another. Experimental results on logic circuits are shown which are superior to those obtained by the method presented by T. Fujii, et al. (ibid., vol.CAD-6, no.3, p.159-64, March 1987).>

This paper deals with the optimum assignment of job modules onto array processors. In array processors it is important to assign job modules onto processors such that the modules that communicate with each other are assigned to adjacent processors, because communication overhead increases as communications occur between processors that are remotely connected. We propose an efficient algorithm to solve this assignment problem for a specific array of processors. The algorithm reduces the quadratic problem to a solvable linear problem that produces a good, but not necessarily optimal solution. This is followed by a phase of iterations in which the solution is improved by small perturbation of the assignment.

This paper introduces a graph space that shows concisely the relative weights among combinations of vertices of a given hypergraph. (A hypergraph is a graph in which one edge may connect two or more vertices.) The hypergraph is represented by a collection of points in graph space such that the distance between vertices in graph space reflects the weights of the edges between vertices of the original hypergraph. Vertices of the hypergraph that are connected by edges with large weights are mapped to nearby points in graph space. Thus, graph space reveals properties of the connectivity of vertices in the hypergraph. A natural application of graph space is the placement of modules in computer systems since strongly coupled modules are transformed into nearby points in graph space. The graph of the airlines network in the United States is taken as an example of a hypergraph, and the paper illustrates the corresponding graph space.