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Janaki Akella

dblp:39/2522 · DBLP profile ↗
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5ranked-venue papers
3as first author
0since 2021 · last 1992
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 2 first-authorSoftware engineering, systems software and programming languages · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Electronic design automation · 65% Performance modeling and evaluation · 35%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
logic synthesis
0.021989
Addendum to 'A kernel-finding state assignment algorithm for multi-level logic' · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
A Kernel-Finding State Assignment Algorithm for Multi-Level Logic · DAC 1988
Electronic design automation › logic synthesis
multilevel logic synthesis
0.021989
Addendum to 'A kernel-finding state assignment algorithm for multi-level logic' · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
A Kernel-Finding State Assignment Algorithm for Multi-Level Logic · DAC 1988
Electronic design automation › logic synthesis
state assignment
0.021989
Addendum to 'A kernel-finding state assignment algorithm for multi-level logic' · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
A Kernel-Finding State Assignment Algorithm for Multi-Level Logic · DAC 1988
Performance modeling and evaluation › storage performance evaluation
i/o subsystem modeling
0.011991
Modeling and Measurement of the Impact of Input/Output on System Performance · ISCA 1991
Performance modeling and evaluation › system modeling
system performance modeling
0.011991
Modeling and Measurement of the Impact of Input/Output on System Performance · ISCA 1991
Performance modeling and evaluation
workload characterization
0.011991
Modeling and Measurement of the Impact of Input/Output on System Performance · ISCA 1991

Methods — techniques the papers use, named apart from their topics

queueing model · 0.0hardware measurement · 0.0state assignment algorithm · 0.0logic optimization · 0.0kernel finding · 0.0
YearPublicationVenuePosition
1992 Concurrent engineering: a prototyping case study
abstract
Vuman is a wearable portable computer used for navigation through electronic blueprints. Thirty working units of Vuman were designed and manufactured from system concept using a concurrent engineering design environment. The authors describe the steps in prototyping Vuman, using the suite of synthesis and analysis tools in the electronic and mechanical domains which comprise the concurrent engineering design environment. Some unforeseen problems and their proposed solutions are discussed.>
Janaki Akella, Allen H. Dutoit, Daniel P. Siewiorek
RSP1
1991 Synthesizing Converters Between Finite State Protocols
abstract
A general approach for synthesizing inter-process communication devices by adapting labeled transition systems is proposed. An approach is also proposed to generate the finite state machine representing the protocol converter. It is assumed that the data path of the protocol converter is already given. The approach is illustrated by generating the communication process between a four phase master and a two phase slave.>
Janaki Akella, Kenneth L. McMillan
ICCD1
1991 Modeling and Measurement of the Impact of Input/Output on System Performance
abstract
The input/otrtput (1/0) subsystem is often the bottleneck in high performance computer systems where the CPU/Memory technology has been pushed to the limit.But recent microprocessor and workstation speeds ae beginning to shift the system balance to the point that 1/0 is becoming the bottleneck even in mid-range and low-end systems.In this work the 1/0 subsystem's impact on system performartce is shown by modeling the relative performance of VAX uniprocessors with and without enhancement in the 1/0 subsystem.Tradhional system performance models were enhanced to include the effect of the I/O subsystem.The parameters modeling the I/O subsystem's effect were identified as D[,O (the number of I/O bytes transferred per instruction executed by the CPU), trl,O (the &ansfer time per I/O byte), and Wq (the waiting time in the I/O subsystem).These parameters were measured on a VAX1 1/780 system by using special purpose hardware and were used to calibrate the enhanced system performance model.It is interesting to note that these measurements indicate that contemporary systems require a factor of eight increase over the I/O bandwidth requirement stated by the Amdhal-Case rule.
Janaki Akella, Daniel P. Siewiorek
ISCA1
1989 Addendum to 'A kernel-finding state assignment algorithm for multi-level logic'
abstract
Two new sets of results are presented that extend work on state assignment for multilevel logic implementation previously reported by the authors (see Proc. IEEE/ACM 25th Design Autom Conf., p.433-8, 1988). Results are presented for several state assignment algorithms that were compared using an improved logic optimization method. The resulting logic implementations were smaller in absolute size and showed considerably more variation in random state assignment than in previous experiments. A new set of experiments that compare state assignment implementations in two-level and multilevel implementations using randomly generated state assignments is reported. These experiments show that, for the benchmark set used, a state assignment that gives a good two-level implementation also gives a good multilevel implementation.>
Marilyn Wolf, Kurt Keutzer, Janaki Akella
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3
1988 A Kernel-Finding State Assignment Algorithm for Multi-Level Logic
Marilyn Wolf, Kurt Keutzer, Janaki Akella
DAC3