Programmable logic arrays (PLAs) present an alternative to logic-gate based design. We propose the transistor level structure of a PLA for single-rail asynchronous applications. The geometrically regular layout together with the deployment of dynamic logic help us fine-tune the PLA to enhance its resistance to side-channel attacks, while parity prediction and checking is employed to protect against malicious fault injection. Finally, we demonstrate how our PLAs can be used as building blocks of large-scale systems with good security characteristics, when combined with special return-to-zero asynchronous latches

In this paper we demonstrate how error-correcting addition and multiplication can be performed using self-checking modules. Our technique is based on the observation that a suitably designed full adder under the presence of any single stuck-at fault produces the fault-free complement of the desired output when fed by the complement of its functional input. We initially apply conventional parity-based error detection in arithmetic modules; upon detection of a fault, this is followed by input inversion, recomputation, and suitable output inversion. We present adder, register and multiplier designs that can be used in this context. We also design a large-scale circuit using this technique (an elliptical filter), outlining the area savings with respect to traditional triple modular redundancy

We consider the problem of designing self-checking controllers for controller/datapath architectures. We introduce the concept of intrinsically secure states. We present six alternative schemes based on parity checking, on 1-out-of-n checking, as well as on the observation that a self-checking sequential datapath can also be employed for control path self-checking by exploiting the concept of intrinsically secure control states. A high-level synthesis tool has been modified to automatically insert self-checking controllers and datapath units and is able to trade this self-checking property against other design objectives. We discuss the properties of each configuration and present experimental results and conclusions

Several researchers have recently implemented on-line testability in the form of duplication-based self-checking digital system design, early in the design process. The authors consider the on-line testability within the optimization phase of iterative, cost function-driven high-level synthesis, such that self-checking resources are inserted automatically without any modification of the source behavioral hardware description language code. This is enabled by introducing a metric for the on-line testability. A new variation of duplication (namely inversion testing) is also proposed and used, providing the system with an additional degree of freedom for minimizing hardware overheads associated with test resource insertion. Considering the on-line testability within the synthesis process facilitates fast and painless design space exploration, resulting in a versatile high-level-synthesis process, capable of producing alternative realizations according to the designer's directions, for alternative target technologies. Finally, the fault escape probability of the overall scheme is discussed theoretically and evaluated experimentally

We consider the problem of designing self-checking controllers for applications with sequential datapaths. Firstly we compare encoded and unencoded (one-hot) controller implementations and we argue that self-checking of encoded control signals is not sufficient in terms of testability. Subsequently, we present four alternative controller self-checking schemes, based both on parity and on the observation that a self-checking data path can be employed for control path self-checking as well, by exploiting intrinsically secure control states. We discuss the properties of each of them, and present a few experimental results.

Having to cope with the continuously increasing complexity of modern digital systems, hardware designers are considering more and more seriously language based methodologies for parts of their designs. Last year the introduction of a new language for hardware descriptions, the SystemC C++ class library, initiated a closer relationship between software and hardware descriptions and development tools. This paper presents a synthesis environment and the corresponding synthesis methodology, based on traditional compiler generation techniques, which incorporate SystemC, VHDL and Verilog to transform existing algorithmic software models into hardware system implementations. Following this approach, reusability of software components is introduced in the hardware world and time-to-market is decreased, as shown by experimental results.