Growing on-chip wire delays will cause many future microarchitectures to be distributed, in which hardware resources within a single processor become nodes on one or more switched micronetworks. Since large processor cores will require multiple clock cycles to traverse, control must be distributed, not centralized. This paper describes the control protocols in the TRIPS processor, a distributed, tiled microarchitecture that supports dynamic execution. It details each of the five types of reused tiles that compose the processor, the control and data networks that connect them, and the distributed microarchitectural protocols that implement instruction fetch, execution, flush, and commit. We also describe the physical design issues that arose when implementing the microarchitecture in a 170M transistor, 130nm ASIC prototype chip composed of two 16-wide issue distributed processor cores and a distributed 1MB non-uniform (NUCA) on-chip memory system

Output queued switches are appealing because they have better latency and throughput than input queued switches. However, they are difficult to build: a direct implementation of an N/spl times/N output-queued switch requires the switching fabric and the packet memories at the outputs to run at N times the line rate. Attempts have been made to implement output queuing with slow components, e.g., by having memories at both inputs and outputs running at twice the line rate. In these approaches, even though the packet memory speed is reduced, the scheduler time complexity is high - at least /spl Omega/(N). We show that idealized output queuing can be simulated in a shared memory architecture with (3N-2) packet memories running at the line rate, using a scheduling algorithm whose time complexity is O(log/sup 2/ N) on a parallel random access machine (PRAM). The number of processing elements and memory cells used by the PRAM are a small multiple of the size of the idealized switch.