The central topic of this paper is the implementation of binary adders with threshold logic using a new methodology that introduces two innovations: the use of the input and output carries of each bit for obtaining all the sum bits and a modification of the classic carry lookahead adder technique that allows us to obtain the expressions of the generation and propagation carries in a more appropriate way for threshold logic. In this way, it has been possible to systematize the process of design of a binary adder with threshold logic relating all its important parameters: number of bits of the operands, depth, size, maximum fan-in, and maximum weight. The results obtained are an improvement on those published to date and are summarized as follows: Depth 2 adder: s=2n, w/sub max/=2/sup n/, f/sub max/=2n+1. Depth 3 adder: s=4n-2[n/[/spl radic/n]], w/sub max/=2[n/[/spl radic/n]], f/sub max/=2[n/[/spl radic/n]]+1. Depth d adder (asymptotic behavior): s=O(n), w/sub max/=O(2/sup d-1/spl radic/n/), f/sub max/=O(/sup d-1/spl radic/n/). If the weights are bounded by w/sub max/:n/sub max/=O(log/sup d-1/ w/sub max/), d/sub min/=O(log n/log(log w/sub max/)).

We present in this paper new types of digital comparator circuits based on clocked cross-coupled inverters. They are digital circuits but they are implemented with analogical techniques. Therefore they have different sizes. The circuits are fast and small compared with traditional implementations.