The analysis and development of ATM network traffic control algorithms is often performed using theoretical traffic models. Algorithms for traffic shaping, policing, flow control, and switch architectures have been proposed based on these models. While the models help to obtain preliminary solutions, the success and validity of the proposed algorithm will be a function of how close the assumed models resemble real traffic patterns. The paper presents ATMTraP, an experimental prototype asynchronous transfer mode traffic and performance measurement tool which could be used in the characterization of sources and elements that form the ATM network. ATMTraP has been used in the Nectar Gigabit Testbed to collect preliminary traffic statistics from sources, such as, a Cray C-90 supercomputer, Sun workstations, and an iWARP systolic array.

The authors examine the physical design issues associated with terabit/second switching systems, particularly with regard to the customer access portion of the switch. They determine the physical design requirements in the areas of backplane interconnections, integrated circuit packaging, and circuit board technology and identify areas where existing- or near-future physical design technologies are inadequate to meet the requirements of this application. A new 3D interconnection architecture that solves some of the problems encountered at the backplane level is suggested. It is also suggested that multichip module technology will help meet some of the speed and density requirements at the chip packaging level. Some of the system-level consequences of the proposed model are discussed.>

A crosspoint-switching chip that can switch bipolar, alternate mark inversion encoded (AMI) signals directly, is described. AMI encoding is a form of ternary, return-to-zero (RZ) coding where a binary zero is represented by an absence of a pulse and ones are represented with an alternating sequence of positive and negative pulses. Bipolar signals are used widely in interoffice telecommunications such as the T1, T1C, T2, and T3 digital transmission systems. The switching chip has 16 input and 16 output channels. Control of the chip allows any input to be connected to any output or outputs, providing a nonblocking connection. The architecture allows for expansion of the crosspoint array by paralleling several chips. The chip, fabricated using a standard 3- mu m CMOS technology, is capable of handling data rates up to 15 Mb/s per channel, has about 17000 transistors, and has an area of about 32.5 mm/sup 2/.>