Counterfeit products have been a major concern in global market. There are many procedures for preventing the counterfeiting of goods, such as holograms, tamper-resistant packaging etc. However, there is still a rising trend in counterfeit goods. With the emergence of RFID systems, supply chain management is able to detect counterfeit products relatively easily. Existing techniques generally involve a centralized database and can only be implemented in an online scenario. This deprives the individual customers of using any authentication mechanism while making purchases due to the infeasibility of accessing a central database. In this paper, we analyze a recently published semi-offline scheme proposed by Alex et al. We identify limitations and weaknesses in this scheme and suggest solutions. We modify the framework to remove the main weakness and extend it to the consumer level so that a consumer can determine the legitimacy of a product. This involves Near Field Communication technology (NFC) which is now widely available in cell phones - the consumer's cell phone acts as an RFID reader and detects counterfeit products. Our solution is completely offline as it does not require a central database for product authentication. It is based on Public Key Cryptography (PKC) and a Public Key Infrastructure (PKI). It offers dual layer authentication mechanisms to customers, visual and cryptographic, without accessing the supplier's database. The main beneficiary of the proposed framework is the consumer who uses the Internet for online shopping and can authenticate a product reliably after delivery. Our scheme is stand-alone and does not require the transfer of any secret values from a centralized authority.

Recent research has demonstrated the vulnerability of certain smart card architectures to power and electromagnetic analysis when multiplier operations are insufficiently shielded from external monitoring. In this paper several standard multipliers are investigated in more detail in order to provide the foundation for understanding potential weaknesses and enabling the subsequent successful repair of those systems. A model is built which accurately predicts power use as a function of the Hamming weights of inputs without the combinatorial explosion of exhaustive simulation. This confirms that power use is indeed data dependent at least for those multipliers. Laboratory experiments confirm that EMR also corresponds closely to these power predictions over a wide range of frequencies.

We propose to relax the restricted form of faithful rounding used in prior 32 bit logarithmic number system (LNS) implementations. Unrestricted faithful rounding yields three- to six-fold savings in VLSI ROM size (or four- to six-fold savings in FPGA table size) with only a modest increase in error. This can be acceptable for the DSP and multimedia applications in which the non-standard LNS is a candidate for adoption. Such applications are cost sensitive, and the tremendous cost reduction of the LNS model proposed should argue very favourably for its adoption.

Comprehensive testing of any implementation of the RSA cryptosystem requires the use of a number of moduli with specific properties. It is shown how to generate a sufficient variety of these to enable testing which will justify high confidence in the correctness of both the design and the operation of hardware implementations. The tests avoid the necessity of another implementation for comparison. Many of these moduli are also suitable for testing software implementations. Furthermore, the methods apply equally well to other similar modular arithmetic based cryptosystems which use exponentiation, such as Diffie-Helman key exchange.

We propose a practical technique to compile left-to-right pattern-matching of prioritised overlapping function definitions in equational languages to a matching automaton from which efficient code can be derived. First, a matching table is constructed using a compilation method similar to the technique that YACC employs to generate parsing tables. The matching table obtained allows for the pattern-matching process to be performed without any backtracking. Then, the known information about right sides of the equations is inserted in the matching table in order to speed-up the pattern-matching process. Most of the discussion assumes that the processed pattern set is left-linear, the non-linear case being handled by an additional pass following the matching stage. Copyright © 1999 John Wiley & Sons, Ltd.

Exponentiation may be performed faster than the traditional square and multiply method by iteratively reducing the exponent module numbers which, as exponents themselves, require few multiplications. This mainly includes those with few nonzero bits. For a suitable choice of such divisors, the resulting mixed basis representation of the exponent reduces the expected number of nonsquaring multiplications by over half at the cost of a single extra register. Preprocessing effort depends entirely on the exponent and can be kept down to the work saved in a single exponentiation. Moreover, no precomputed look-up tables are required, so the method is especially applicable where space is at a premium. In particular, it outperforms the instance of the m-ary method which uses the same space. However, for 512-bit exponents, it beats every instance of the m-ary method, achieving well under 635 multiplications on average. Both hardware and software implementations of the RSA crypto-system can benefit from this algorithm.

Exponentiation may be performed faster than the traditional square-and-multiply method by iteratively reducing the exponent modulo numbers which themselves require few multiplications, such as those with few non-zero bits. For a suitable choice of such divisors, this reduces the expected number of non-squaring multiplications by over half at the cost of a single extra register. The method is applicable to exponentiation in any multiplicative group where squaring is as expensive as multiplication and not cheaper than integer division. In particular, both hardware and software implementations of the RSA crypto-system can benefit.

The value of using a higher radix for modular multiplication in the context of RSA is investigated. The main conclusion is that for algorithms which perform the multiplication via repeated addition, there is, broadly speaking, a direct trade-off between space and time provided by change of radix. Thus chip area utilized is roughly proportional to speed. However, initially, as the radix is increased from 2, there is a short-lived increase in speed greater than the extra area used.

Hardware is described for implementing the fast modular multiplication algorithm developed by P.L. Montgomery (1985). Comparison with previous techniques shows that this algorithm is up to twice as fast as the best currently available and is more suitable for alternative architectures. The gain in speed arises from the faster clock that results from simpler combinational logic.>

A systolic array for modular multiplication is presented using the ideally suited algorithm of P.L. Montgomery (1985). Throughput is one modular multiplication every clock cycle, with a latency of 2n+2 cycles for multiplicands having n digits. Its main use would be where many consecutive multiplications are done, as in RSA cryptosystems.>