The very first Design Automation Conference was held in 1964 when computers were programmed with punch cards. The initial topics were related to automated Printed Circuit Board design, cell placement, and early attempts at transient circuit analysis. The next decades saw the introduction of key graph algorithms and numerical analysis methods. Optimal algorithms and more practical heuristic methods were published. The 1980ies saw the advent of simulated annealing, a universal heuristic optimization method that found many applications. The next decade introduced powerful numerical placement methods for millions of cells. Soon after, physical synthesis was born by combining several incremental synthesis and analysis tools. Today's commercial EDA tools run a very complex design flow that chains together hundreds of algorithms that were developed over 60 decades. Most effort is in the careful fine-tuning of parameters and addressing the complex - and often surprising - algorithmic interactions. This is a difficult trial-and-error process, driven by a small set of benchmarks. Machine Learning methods will take some of the human tuning efforts out of this loop. Some have already found their way in commercial tools. It will take a while before a Machine Learning method fully replaces a 'traditional' EDA algorithm. Each method in the flow has a limited sweet spot and is often run-time critical. On the other hand, conventional algorithms leave only insignificant opportunities for speed up through parallelism. Machine Learning methods may provide the only viable way to unlock the potential of massive cloud computing resources.

Solving 3-D partial differential equations in a Finite Element model is computationally intensive and requires extremely high memory and communication bandwidth. This paper describes a novel way where the Finite Element mesh points of varying resolution are mapped on a large 2-D homogenous array of processors. Cerebras developed a novel supercomputer that is powered by a 21.5cm by 21.5cm Wafer-Scale Engine (WSE) with 850,000 programmable compute cores. With 2.6 trillion transistors in a 7nm process this is by far the largest chip in the world. It is structured as a regular array of 800 by 1060 identical processing elements, each with its own local fast SRAM memory and direct high bandwidth connection to its neighboring cores. For the 2021 ISPD competition we propose a challenge to optimize placement of computational physics problems to achieve the highest possible performance on the Cerebras supercomputer. The objectives are to maximize performance and accuracy by optimizing the mapping of the problem to cores in the system. This involves partitioning and placement algorithms.

This paper introduces a special case of the floorplanning problem for optimizing neural networks to run on a wafer-scale computing engine. From a compute perspective, neural networks can be represented by a deeply layered structure of compute kernels. During the training of a neural network, gradient descent is used to determine the weight factors. Each layer then uses a local weight tensor to transform "activations" and "gradients" that are shared among connected kernels according to the topology of the network. This process is computationally intensive and requires high memory and communication bandwidth. Cerebras has developed a novel computer system designed for this work that is powered by a 21.5cm by 21.5cm wafer-scale processor with 400,000 programmable compute cores. It is structured as a regular array of 633 by 633 processing elements, each with its own local high bandwidth SRAM memory and direct high bandwidth connection to its neighboring cores. In addition to supporting traditional execution models for neural network training and inference, this engine has a unique capability to compile and compute every layer of a complete neural network simultaneously. Mapping a neural network in this fashion onto Cerebras' Wafer-Scale Engine (WSE) is reminiscent of the traditional floorplanning problem in physical design. A kernel ends up as a rectangle of x by y compute elements. These are the flexible blocks that need to be placed to optimize performance. This paper describes an ISPD 2020 challenge to develop algorithms and heuristics that produce compiled neural networks that achieve the highest possible performance on the Cerebras WSE.

EDA engineers automate IC design while optimizing speed, power and cost. Though automotive design also has objectives for speed, power and cost, the process is not as well automated. Automotive powertrain engineering has progressed dramatically due to the push for cleaner environment and the pull of more affordable electronics and batteries. This is resulting in ever more electric and efficient gasoline-electric hybrid cars on the road. This presentation will look at what "drives" the design optimization of the drive train from the energy source all the way down to where the rubber meets the road. This includes relevant aspects such as energy efficiency, emissions and practicality of gasoline and electrical drivetrains in modern cars. They use "regenerative" braking that recovers approximately 70% of the kinetic energy. The new generation of hybrid-electric transmissions can hit the fuel consumption "sweet spot" while delivering a fun high-torque driving experience. This is done by dynamically blending the power of an internal combustion engine with two electric motors using planetary gears. A modern plug-in hybrid may have 5 different drive modes, each optimizing the energy flow for maximum efficiency.

Engineering is the science of converting theory into practice. It is also the "art" of technical design. Among all engineering disciplines semiconductor electronic design has pushed the limits of true design automation far further than any other technical discipline. Armies of engineers were needed to design the Airbus A380, yet it is morphologically identical to a Boeing 747 designed using slide rulers 50 years ago. Contrast that to IC designers who build a billion-component chip from idea to hardware in just a few months. And they do that while the scale of the design reliably doubles every 2 years. Enabling this unprecedented degree of electronic design automation are a set of algorithms chained together as a flow that crosses several design abstractions down to a physical circuit mask pattern. During his illustrious career Ralph Otten's ideas and vision have shaped design automation in significant ways: by contributing algorithms and by defining methodologies to safely cross abstraction levels using automated tools. Ralph Otten's career parallels the development of circuit design flows from birth to mature flows. He developed the very first floorplan representations and worked on the very first logic synthesis flows (then called a "silicon compiler"). As director of education Ralph has set new directions, celebrating the strong points of the broader Electrical Engineering discipline. This presentation will address the the impact he has putting putting EDA on the map as an engineering discipline with a solid theoretical foundation. As a result, visionary-yet-small university projects matured into a coherent industrial-strength tools flows.

A 'Physical Synthesis' design flow combines logical synthesis techniques with layout synthesis algorithms. This flow is in flux due to extreme uncertainty of the delays in the latest process nodes. The resulting flow is an intricate combination of a design steps and analysis runs, the tuning of which requires constant attention. Rather than addressing the individual algorithms, this presentation addresses the general structure of a successful physical synthesis design flow.

A practical Physical Design flow is an intricate chain of many algorithms. Assorted placers and routers are interspersed with incremental logical synthesis algorithms that patch up timing. The overall goal is to address a plethora of design objectives simultaneously such as LVS/DRC correctness, speed, area, power and yield. Each new technology node adds additional complications to flow. Increased crosstalk sensitivity, and tighter power and yield requirements are currently causing havoc in 28nm.

Statistical analysis is a fundamental method in analysis, design, and optimization of large systems with uncertainties. It is being applied in drug development, analyzing financial markets, search for new oil fields, and many more areas. As the silicon process technology scales to its limits, uncertainty plays an increasing role and has made its way into tools such as yield analysis, statistical time analysis, etc. In this educational panel, we will start with a short tutorial on Monte Carlo methods including their use in EDA. Three experts from distinct application fields will then follow and discuss their experience in using Monte Carlo methods for solving large-scale problems in their domain. It may come as a surprise to some attendees of DAC to learn how much commonality there is between methods used in EDA and other field that seem far-fetched.

Growing complexity of multiprocessor systems on chip (MP-SoC) requires future communication resources that can only be met by highly scalable architectures. Networks-on-Chip (NoCs) offer this scalability and other advantages like modularity, quality-of-service (QoS), possibly smaller area footprint and lower power dissipation. Although many papers describe the advantages of NoCs and describe techniques to apply NoCs on certain application domains, few have actually employed the complete design chain to make a netlist level implementation and area comparison (Steenhof et al., 2006) and (Angiolini et al., 2006). This paper describes the application of the AEligthereal NoC to an existing bus-based MP-SoC design and an area comparison with the original interconnects structure down to netlist level

The scaling of interconnect technology hits a red brick wall: interconnect delay and power do not follow Moore's law any more. The use of new materials like Cu and low-k alleviated the problem temporarily, but physical limits are being hit. What does this mean for system level design? The session starts with an embedded tutorial, given by an interconnect semiconductor technology expert, explaining the physics behind the interconnect problem and the degrees of freedom semiconductor technology offers system designers. Panelists will then express their thoughts and discuss with you how the interconnect problem can be solved by taking these degrees of freedom into account at the system design level. Views from industrial designers, CAD vendors, IC manufacturers and researchers will be presented.

Congestion is a fundamental problem in VLSI design flows. Typically, it is handled by feeding back density information to the placers and routers. Fast and accurate congestion estimation is key in order to obtain a design flow with less iterations and higher predictability.Fast congestion prediction is based on an accurate approximation of the actual routing engine. In this paper we show experimentally that the number of two-pin nets with more than two bends in the actual router is negligible. It is also established that the ratio between the number of L-shapes and Z-shapes is more or less a constant.A fast and accurate algorithm for congestion prediction is developed. The above observations are translated into probabilities, that are used to "smear" out a net over its possible realizations. Extensive experimental evidence is provided using industrial designs.

Overview Two years ago, DAC-2001 attendees enjoyed a thrilling debatepanel, “Who’s Got Nanometer Design Under Control?”, pitting sky-is-falling Physics die-hards against not-to-worry Methodology gurus. Then, the DAC audience overwhelmingly voted the match for the Methodologists. Now, we've just gone through the biggest business downturn in the industry's history, and we're hearing more and more about chip failures due to 130nm physical effects. Both physics and economics are a lot worse than we thought two years ago. Where are those simple, correct-by-construction methodologies for signal integrity, power integrity, low-power, etc. that we were promised? Were we bamboozled by glib promises from those Methodologists? In this session, we bring back the panelists from two years ago, not for another debate, but to hear well-reasoned perspectives on how to prioritize spending to address nanometer design challenges. Yes, methodology can solve any problem – but now we want to know which problems, in what priority order, at what cost. The panel will address the following questions. • What are the economic impacts and significance of the key nanometer design challenges, relative to each other? • Which nanometer design problems merit responsible R&D investment, in what amounts and proportion? • What is the likelihood of success, both near-term and longterm, in solving key nanometer design challenges? • Where will the answers come from? To keep the discussion very concrete, each panelist will be given a $100 budget, and must defend their allocation of this budget to attack various design problems. Where should the $100 be spent? The audience will determine the best-reasoned allocation, and the winning panelist keeps all the money.

As chip design becomes ever more complex, fewer design teams are succeeding. Who's to blame? On one hand, tools are hard to use, buggy, not interoperable, and have missing functionality. On the other hand, there is a wide range of engineering skills within the user population, and tools can be abused within flawed methodologies. This panel will quantify and prioritize the key gaps, including interoperability, that must be addressed on both sides.

Advancing process technology will necessitate and even more rigorous automation of the IC design trajectory. The design scale will increase with Moore's law, approaching 1,000,000,000 transistors in the coming years. This enables the design of SoC systems with complexities unprecedented unhuman history. At the same time the physics of silicon manufacturing is increasing the 'silicon complexity'. Additional design steps are required to address cross talk, voltage drop, antenna rules and others. Much more so than in previous technology nodes, the effects of parasitics must be addressed at various stages of the IC design flow. Nothing less than a full automation of the silicon complexity issues is required to stop the design productivity gap from growing.

No abstract available.

It's been one year since Richard Goering told us that the EDA RTL-to-GDSII world was about to change. What have we learned? Who's winning, and who's not? This panel, consisting of the leading large and upcoming players in this space, will deliver concrete data to differentiate leading approaches to achieving design closure. Does the solution lie in raw speed and RTL optimization, with the synthesis-place-route back end just a commodity? Does the solution lie in new metrics for design convergence, and symmetric multiprocessing platforms for efficiency? Does the solution lie in a holistic, unified architecture of data model and tools? Or does the solution lie in extensions and unifications of existing production-proven logic, timing, and layout optimization technologies? A hard-hitting panel session will reveal the answers!

No abstract available.

An n-layer gridless channel router is presented. Instead of the commonly used grid it uses a set of contours as a routing framework. The contours, together with a set of reserved areas, present short circuits and ensure routability of all nets. A compact routing can be expected, since the framework is a very adequate model of the physical channel. It is shown that this router is also versatile enough to handle the classic vertical constraint problem. The inherent flexibility enables a design rule driven tradeoff between the number of vias, the wire length, and the channel height. The behavior of the algorithm has been investigated for many different channels, including the well-known difficult example and its recent derivatives. Very competitive results have been achieved for channel height and via count.>