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Maheswara R. Samatham

dblp:39/72 · DBLP profile ↗
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3ranked-venue papers
3as first author
0since 2021 · last 1989
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 first-authorSoftware engineering, systems software and programming languages · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Interconnection networks and networks-on-chip · 74% Electronic design automation · 14% Hardware reliability and fault tolerance · 10%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › network topology › low-diameter topology
de bruijn network		 0.031989
The De Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI · IEEE Trans. Computers 1989
The de Bruijn Multiprocessor Network: A Versatile Sorting Network · ISCA 1985
A Multiprocessor Network Suitable for Single-Chip VLSI Implementation · ISCA 1984
Interconnection networks and networks-on-chip
sorting network		 0.021989
The De Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI · IEEE Trans. Computers 1989
The de Bruijn Multiprocessor Network: A Versatile Sorting Network · ISCA 1985
Interconnection networks and networks-on-chip
multiprocessor interconnection		 0.021989
The De Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI · IEEE Trans. Computers 1989
A Multiprocessor Network Suitable for Single-Chip VLSI Implementation · ISCA 1984
Electronic design automation › physical design
VLSI layout		 0.021989
The De Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI · IEEE Trans. Computers 1989
A Multiprocessor Network Suitable for Single-Chip VLSI Implementation · ISCA 1984
Interconnection networks and networks-on-chip
network topology		 0.011989
The De Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI · IEEE Trans. Computers 1989
Hardware reliability and fault tolerance
network fault tolerance		 0.021989
The de Bruijn Multiprocessor Network: A Versatile Sorting Network · ISCA 1985
The De Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI · IEEE Trans. Computers 1989
Parallel and multicore computing › parallel algorithms › sorting
parallel sorting		 0.011985
The de Bruijn Multiprocessor Network: A Versatile Sorting Network · ISCA 1985
Interconnection networks and networks-on-chip
network layout		 0.011984
A Multiprocessor Network Suitable for Single-Chip VLSI Implementation · ISCA 1984

Methods — techniques the papers use, named apart from their topics

de bruijn graph · 0.0VLSI layout · 0.0FFT · 0.0
YearPublicationVenuePosition
1989 The De Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI
abstract
It is shown that the binary de Bruijn multiprocessor network (BDM) can solve a wide variety of classes of problems. The BDM admits an N-node linear array, an N-node ring, (N-1)-node complete binary trees, ((3N/4)-2)-node tree machines, and an N-node one-step shuffle-exchange network, where N (=2/sup k/, k an integer) is the total number of nodes. The de Bruijn multiprocessor networks are proved to be fault-tolerant as well as extensible. A tight lower bound of the VLSI layout area of the BDM is derived; a procedure for an area-optimal VLSI layout is also described. It is demonstrated that the BDM is more versatile than the shuffle-exchange and the cube-connected cycles. Recent work has classified sorting architectures into (1) sequential input/sequential output, (2) parallel input/sequential output, (3) parallel input/parallel output, (4) sequential input/parallel output, and (5) hybrid input/hybrid output. It is demonstrated that the de Bruijn multiprocessor networks can sort data items in all of the abovementioned categories. No other network which can sort data items in all the categories is known.>
Maheswara R. Samatham, Dhiraj K. Pradhan
 IEEE Trans. Computers1
1985 The de Bruijn Multiprocessor Network: A Versatile Sorting Network
abstract
Recent work [I] has classified sorting architectures as: (A) Sequential input/Sequentlal output, (B) Parallel input/Sequentlal output, (C) Parallel Input/Parallel output, (D) Sequential input/Parallel output and (E) Hybrid input/Hybrld output.The classification is based, not only on the I/O method, but also on the interconnection network, the sorting algorithm and the type of keys used.This paper demonstrates that the architectures based on the undirected de BrulJn graphs (DGs) can sort data items in all of the above mentioned categories.To the best of our knowledge, no other single network which can sort data items in all the categories is known.Sorting algorithms and time complexities that correspond to each of these categories are given here.It is shown that these architectures can achieve the previously known best upper bound times, in all of the categories.Also, it is proven that they work as sorting networks, even in the presence of some faults.
Maheswara R. Samatham, Dhiraj K. Pradhan
 ISCA1
1984 A Multiprocessor Network Suitable for Single-Chip VLSI Implementation
abstract
This paper presents a multiprocessor network architecture suitable for VLSI implementation. The proposed class of architectures is based on De Bruijn graphs which are distinct from the well-studied shuffle-exchange graphs. Compared to these latter De Bruijn graphs possess a smaller diameter and a greater fault-tolerance. The proposed architectures are shown to be suitable for efficient execution of parallel algorithms such as the N-point fast Fourier transform (FFT). It is shown that any VLSI layout of the proposed networks requires an area of atleast Ω(N2/logN), thus, providing a lower bound which is greater than that for shuffle-exchange graphs. Two procedures for laying out these networks on a VLSI chip are presented. The first procedure produces an O(N2/logN)-area layout and has a time complexity of O(N). The second procedure also produces an O(N2/logN)-area layout with good aspect ratio close to unity (for small N).
Maheswara R. Samatham, Dhiraj K. Pradhan
 ISCA1