We have devised an object oriented DBMS called Jasmine for advanced applications. The paper describes the implementation, application and extension of Jasmine in detail. We focus on the impact of the design of its object oriented model and language on database implementation technology. We describe what part of traditional relational database technology we extend to handle object oriented features such as object identifiers, complex objects, class hierarchies, and methods. We introduce nested relations to efficiently store and access clustered complex objects. We use hash based methods to efficiently access nonclustered complex objects. We provide user defined functions directly evaluated on page buffers to efficiently process method invocation. We devise object oriented optimization of queries including class hierarchies, complex objects, and method invocation. We incorporate dedicated object buffering to allow efficient access to objects through object identifiers. We also describe nontrivial applications of Jasmine and discuss the validity of object oriented databases. We focus on a constraint management facility, which can be implemented by taking advantage of the extensibility of Jasmine. The facility includes constraint rules, called design goals, for automatic database population required by engineering applications. Finally, we describe a view facility for schema integration also needed by engineering applications in distributed environments. We focus on how we extend Jasmine to implement the facility.

R.E. Bryant proposed a method to handle logic expressions (IEEE Trans. Comp., vol.25, no.8, p.667-91, 1986) which is based on binary decision diagrams (BDD) with restriction; variable ordering ix fixed throughout a diagram. The method is more efficient than other methods proposed so far and depends heavily on variable ordering. A simple but powerful algorithm for variable ordering is developed. The algorithm tries to find a variable ordering which minimizes the number of crosspoints of nets when the circuit diagram is drawn. This is applied to the Boolean comparison of ISCAS benchmark circuits for test pattern generation. The results show that binary decision diagrams (BDD) with the proposed ordering method can verify almost all benchmark circuits in less than several central processor unit (CPU) minutes, which is one hundred times (or more) faster than times reported in the literature. Some techniques for circuit evaluation ordering are also mentioned.>

A method is presented to accelerate test generation, which synthesizes a test-generation circuit S(C, F) that combines the original combinational circuit C (modified by programmable faults F) and peripheral circuits that automatically generate a test of C. The test patterns are generated by searching the inputs to expose faults to the outputs using an ultrahigh-speed simulator (SP).>

This paper presents a CMOS gate-array version of Digital System Design Language/Synthesis eXpert (DDL/SX), a rule-based system for logic circuit synthesis. The system inputs technology-independent functional diagrams, and automatically generates conventional technology-dependent logic diagrams in order to eliminate time-consuming and error-prone tasks in logic design. Because the synthesis process was not clear enough to establish a fixed algorithm, a rule-based approach was adopted to develop the system. This approach made it easy to incrementally improve the system's capabilities by adding, modifying, or deleting design knowledge represented as rules. Experimental use of the system revealed that the automatically generated logic design is almost as good as a manual design, and the design time is reduced by a factor of four.

This paper proposes an interactive logic synthesis system which supports translation from behavioral to gate level. A design's specification described in the register transfer language DDL is translated into abstract objects. They are converted to macros representing logical structure and serving as technology independent goals which guide designers in synthesis phases. The system has knowledge about the technology adopted and can accommodate various know-how and design constraints to support the designer's tasks of PCB partition and logic synthesis. As a result, it greatly relieves designers from tedious tasks and makes it possible to explore alternative designs.

Most existing hardware design verification techniques (logic simulation, symbolic simulation etc.), as well as the design phase, are rather synthetic. This paper discusses an analytic verification technique with examples of its application.