Demo Data from VLDB 2026 / reviewers in the wild / expert
Ian Bratt
dblp:39/803
· DBLP profile ↗
3ranked-venue papers
2as first author
0since 2021 · last 2015
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-authorSoftware engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 70% Interconnection networks and networks-on-chip · 23% Performance modeling and evaluation · 7% |
Topics — the 4 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture
instruction-level parallelism |
0.0 | 1 | 2004 | Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams · ISCA 2004 |
Interconnection networks and networks-on-chip › interprocessor communication
operand transport network |
0.0 | 1 | 2004 | Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams · ISCA 2004 |
Processor architecture and microarchitecture
tiled architecture |
0.0 | 1 | 2004 | Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams · ISCA 2004 |
Performance modeling and evaluation › simulation › architectural simulation
cycle-accurate simulation |
0.0 | 1 | 2004 | Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams · ISCA 2004 |
Methods — techniques the papers use, named apart from their topics
cycle-accurate simulation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2015 | The ARM® Mali-T880 Mobile GPU
Ian Bratt |
Hot Chips Symposium | 1 |
| 2013 | HSA queueing
Ian Bratt |
Hot Chips Symposium | 1 |
| 2004 | Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and StreamsabstractThis paper evaluates the Raw microprocessor. Raw addresses the challenge of building a general-purpose architecture that performs well on a larger class of stream and embedded computing applications than existing microprocessors, while still running existing ILP-based sequential programs with reasonable performance in the face of increasing wire delays. Raw approaches this challenge by implementing plenty of on-chip resources - including logic, wires, and pins - in a tiled arrangement, and exposing them through a new ISA, so that the software can take advantage of these resources for parallel applications. Raw supports both ILP and streams by routing operands between architecturally-exposed functional units over a point-to-point scalar operand network. This network offers low latency for scalar data transport. Raw manages the effect of wire delays by exposing the interconnect and using software to orchestrate both scalar and stream data transport. We have implemented a prototype Raw microprocessor in IBM's 180 nm, 6-layer copper, CMOS 7SF standard-cell ASIC process. We have also implemented ILP and stream compilers. Our evaluation attempts to determine the extent to which Raw succeeds in meeting its goal of serving as a more versatile, general-purpose processor. Central to achieving this goal is Raw's ability to exploit all forms of parallelism, including ILP, DLP, TLP, and Stream parallelism. Specifically, we evaluate the performance of Raw on a diverse set of codes including traditional sequential programs, streaming applications, server workloads and bit-level embedded computation. Our experimental methodology makes use of a cycle-accurate simulator validated against our real hardware. Compared to a 180nm Pentium-III, using commodity PC memory system components, Raw performs within a factor of 2/spl times/ for sequential applications with a very low degree of ILP, about 2/spl times/ to 9/spl times/ better for higher levels of ILP, and 10/spl times/-100/spl times/ better when highly parallel applications are coded in a stream language or optimized by hand. The paper also proposes a new versatility metric and uses it to discuss the generality of Raw. Michael B. Taylor, Walter Lee, Jason E. Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul R. Johnson, Jason Sungtae Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matthew I. Frank, Saman P. Amarasinghe, Anant Agarwal |
ISCA | 5 |