Real-world multivariate time series anomalies are rare and often unlabeled. Additionally, prevailing methods rely on increasingly complex architectures tuned to benchmarks, detecting only fragments of anomalous segments and overstating performance. In this paper, we introduce OracleAD, a simple and interpretable unsupervised framework for multivariate time series anomaly detection. OracleAD encodes each variable’s past sequence into a single causal embedding to jointly predict the present time point and reconstruct the input window, effectively modeling temporal dynamics. These embeddings then undergo self-attention mechanism to project them into a shared latent space and capture spatial relationships. These relationships are not static, since they are modeled by a property that emerges from each variable's temporal dynamics. The projected embeddings are aligned to a Stable Latent Structure (SLS) representing normal-state relationships. Anomalies are identified using a dual scoring mechanism based on prediction error and deviation from the SLS, enabling fine-grained anomaly diagnosis at each time point and across individual variables. Since any noticeable SLS deviation originates from embeddings that violate the learned temporal causality of normal data, OracleAD directly pinpoints the root-cause variables at the embedding level. OracleAD achieves state-of-the-art results across multiple real-world datasets and evaluation protocols, while remaining interpretable through SLS.

A multichannel clock and data recovery (CDR) circuit that employs binary phase detectors (PDs) yet achieves linear loop dynamics is presented. The proposed CDR recovers the linear information of phase errors by exploiting its collaborative timing recovery architecture. Since the collaborative CDR combines the PD outputs of the multiple data streams, a deliberate phase offset can be added to each PD to realize a high-rate oversampling PD without additional PDs. The analysis shows that there exists an optimal spacing between these deliberate phase offsets that maximizes the linearity of the proposed PD for given jitter conditions. Under these conditions, the loop dynamics of a linear, second-order CDR model agree well with the simulated responses even with a finite latency difference between the proportional and integral control paths. The linearized characteristics of the PD and the overall CDR designed for 45-nm CMOS technology are, respectively, verified by using a time-step accurate behavioral simulation.

This paper presents an IEEE 1588-2008 adapter that provides existing Gigabit Ethernet equipment with the functionalities required to clock synchronization on the order of sub-microsecond. To compensate the time error caused by the queuing delays in the Gigabit Ethernet equipment, the adapter measures the residence time and runs the peer delay mechanism for the equipment. Major functional blocks including the clock synchronization cores, Media Access Controls (MACs), and frame buffers have been integrated into a 21 mm2silicon chip in 0.18 μm CMOS process. Experimental results show that the end devices can be synchronized within ±20 ns by simply attaching the proposed IEEE 1588-2008 adapters to the ordinary switches that connects the end devices.