Evaluating the sensitivity of circuits to Single Event Upset (SEU) faults has become increasingly important and challenging due to the growing complexity of circuits. Simulation-based fault injection is time-intensive, particularly for highly complex circuits. This paper proposes a novel approach using Spatio-temporal Graph Convolutional Networks (STGCN) to predict SEU fault propagation results in circuits. By representing circuits’ structure as graphs and integrating temporal features from the simulation workload, STGCNs can learn from these spatio-temporal graphs to identify SEU fault propagation patterns. To validate this method, we test it on six evaluation circuits, achieving a prediction accuracy of 93-99%. Given this performance, to accelerate SEU simulation-based fault injection, we divide SEU faults into three subsets and use a STGCN fine-tuned on the training and validation dataset to predict SEU fault propagation in the test dataset, eliminating the need for simulation and reducing the required time. To identify an efficient dataset separation method, we compare three sampling methods: spatial sampling (sampling flip-flops for injected faults), temporal sampling (sampling time points for fault injection), and hybrid sampling (incorporating both spatial and temporal sampling). The hybrid sampling approach is the most promising, optimizing the trade-off between efficiency and accuracy. This approach reduces simulation time by 50% while maintaining accuracy above 95% on the six evaluation circuits.

The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely, creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks, we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors, this enables us to construct anandstandard cell, which merely consumes the area of two transistors. This leads to a 25% area reduction compared to an equivalent CMOSnandgate. We illustrate achievable area savings with a half-adder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7% smaller area than the equivalent design using standard CMOS gates.

Assessing Single Event Upset (SEU) sensitivity in complex circuits is increasingly important but challenging. This paper proposes an efficient approach using Spatio-temporal Graph Convolutional Networks (STGCN) to predict the results of SEU simulation-based fault injection. Representing circuit structures as graphs and integrating temporal data from the workload's waveform into these graphs, STGCN achieves a 94-96% prediction accuracy on four test circuits.

The adoption of Deep Neural Networks (DNNs) in several domains allows for increased effectiveness in applications that deal with massive data-intensive and complex data inputs. When employed in safety-critical scenarios, such as automotive, aerospace, healthcare, and autonomous robotics, assessing the DNNs' reliability and functional safety is crucial to ensure their correct in-field operation, even in the presence of hardware faults. However, the system complexity and the massive amounts of data to be processed by DNNs prevent the effective adoption of traditional strategies for reliability characterization and for identifying the most fault-sensitive structures. Accurate fault assessment strategies usually require unacceptable computational power and large evaluation times. On the other hand, faster strategies commonly lack accuracy in correctly representing system faults. Consequently, it is necessary to develop effective strategies that trade-off between performance and accuracy. This work analyses three reliability assessment strategies for deep neural networks and their underlying hardware, highlighting the main solutions and challenges in terms of evaluation performance and fault characterization accuracy. We overview different solutions to evaluate the hardware accelerators implementing DNNs at three abstraction levels:$i$) by physically injecting faults on a GPU running DNNs, ii) by performing microarchitectural characterization of GPUs to develop application-accurate error models, and iii) by using structure-aware cross-layer error modeling on DNN hardware accelerators. Our experimental results indicate that accurate error representation requires structural features from the targeted hardware.

Nanometer circuits are becoming increasingly susceptible to soft errors. Selective hardening is a less expensive technique to improve the reliability of circuits because it hardens the critical components instead of hardening an entire circuit. One challenge of selective hardening is efficiently and effectively identifying the critical parts in circuits. Simulation-based fault injection is commonly used but extremely time-consuming, especially for complex circuits. This article proposes an approach based on graph neural networks (GNNs) to identify critical flip-flops in circuits. GNNs can take advantage of the circuit’s structural features and the features of individual flip-flops. To convert the features into abstract data that can be fed into GNNs, we provide a feature extraction method that uses a graph model to represent the relevant features of the circuit. The method converts the target circuit into a graph representing its architecture. The graph also contains features of individual flip-flops extracted from the circuit’s netlist and the value change dump (VCD) waveforms of the test used for fault simulation. Additionally, we extract edge features in the graph to utilize the information on combinational gates on the path between flip-flops. Datasets generated based on two open-source RISC-V cores are used to validate the proposed approach. We compare the performance of different GNNs on them and discuss the contribution of edge features to their performance. Our experiments show that the prediction accuracy increases significantly with edge features. GraphSAGE and SAGE-GCN with edge features perform best among the selected GNNs. The highest accuracy we achieved on Ibex and RI5CY is 97.75% and 98.67%, respectively. We also provide a method to accelerate the process of critical flip-flop identification.

Simulation-based fault injection is a widely used technique for early-stage circuit reliability analysis. However, it consumes significant time, particularly for complex circuits. This paper introduces two Machine Learning (ML) methodologies to predict simulation-based fault injection outcomes at the gate level. The initial approach employs Neural Networks (NNs), extracting structural features from synthesis reports and simulation-related characteristics from Value Change Dump (VCD) waveforms. Nevertheless, NNs are restricted to learning from individual gate attributes. To exploit the comprehensive structure of entire circuits, we propose a method to convert circuits into graphs. This facilitates the utilization of Graph Neural Networks (GNNs) as advanced models, resulting in improved prediction performance. We select six open-source circuits with diverse complexities and functions to validate these methodologies and explore their adaptability across various circuits. Our experiments demonstrate the superior performance of GNNs compared to NNs in terms of prediction accuracy, efficiency in hyperparameter search, and the ability to address imbalanced datasets. Additionally, we investigate the feasibility of deploying the trained models to predict results in new circuits. Based on the experimental outcomes, we present an approach for leveraging the proposed methodology to accelerate simulation-based fault injection.

Electronic systems can be submitted to hostile environments leading to bit-flips or stuck-at faults and, ultimately, a system malfunction or failure. In safety-critical applications, the risks of such events should be managed to prevent injuries or material damage. This paper provides a comprehensive overview of the challenges associated with designing and verifying safe and reliable systems, as well as the potential of the RISC-V architecture in addressing these challenges.We present several state-of-the-art safety and reliability verification techniques in the design phase. These include a highly-automated verification flow, an automated fault injection and analysis tool, and an AI-based fault verification flow. Furthermore, we discuss core hardening and fault mitigation strategies at the design level. We focus on automated SoC hardening using model-driven development and resilient processing based on sensing and prediction for space and avionic applications.By combining these techniques with the inherent flexibility of the RISC-V architecture, designers can develop tailored solutions that balance cost, performance, and fault tolerance to meet the requirements of various safety-critical applications in different safety domains, such as avionics, automotive, and space. The insights and methodologies presented in this paper contribute to the ongoing efforts to improve the dependability of computing systems in safety-critical environments.

Detection and measurement of ionizing radiation is required in a wide range of terrestrial applications, as well as in space missions. For this purpose, special instruments composed of radiation sensors and readout electronics are utilized. As ionizing radiation may affect the operation of electronic systems, radiation hardness is one of the main design requirements for radiation monitoring systems. In this work, we present a concept of a smart multi-sensor radiation monitoring system. The proposed design is based on the results achieved within the framework of EU-funded ELICSIR project. Our solution provides a new perspective on smart radiation monitoring by combining the concepts of self-awareness, self-adaptivity and artificial intelligence. This solution is suitable for applications where long-term autonomous radiation monitoring is required, such as environmental monitoring at terrestrial level or radiation monitoring in space missions.

Due to their flexibility and openness, the RISC-V ISA and processor architectures have emerged as notable contenders in various application domains. Their advantages over commercial solutions have attracted the interest of academia and industry and even led to their planned adoption in aeronautics and space. However, in these demanding environments, system reliability is of paramount importance. To address this issue, this paper presents an overview of several hardware-centric approaches for developing reliable systems based on the parallel-ultra low power (PULP) open-source RISC-V hardware platform. These approaches range from gate-level optimizations to system-level improvements and highlight the versatility of the PULP architecture and its potential as a viable architecture for developing various aerospace platforms.

Solar Particle Events (SPEs) generate cosmic radiation of different magnitude in a time span of several hours or even days. This contributes to an increased probability of higher magnitude Single-Event Upsets (SEUs) occurrence in space applications. It is critical to establish early detection of SEU rate or Soft Error Rate (SRE) changes to enable timely radiation hardening measures. This research paper focuses on the high-accuracy detection of SPEs using the manually collected space data. Additionally, the prediction of SRE increase or decrease was established with the seven widely used supervised machine learning algorithms. Excellent performance of 97.82%, including a high F1-score, was achieved during the presence of SPE using$k$-Nearest Neighbor algorithms.

Measurement of absorbed dose and dose rate is a common task in radiation environments such as space. This is accomplished with the specialized instruments known as radiation dosimeters. Among the most commonly used radiation dosimeters in space missions are those based on the Radiation Sensitive Field Effect Transistors (RADFETs). In this paper, we propose a design concept for a radiation hardened readout system for the real-time measurement of absorbed dose and dose rate with RADFET. The successive switching between the absorbed dose and dose rate readout modes, as well as the subsequent data processing, are performed by the self-adaptive fault-tolerant Multiprocessing System-on-Chip (MPSoC). The integrated framework controller and the real-time monitoring of particle flux with the embedded Static Random Access Memory (SRAM) enable the autonomous selection of operating and fault-tolerant modes, thus achieving the optimal performance under variable radiation conditions.

Cosmic radiation phenomena such as Solar Particle Events cause high radiation flux lasting from hours to days, thus increasing the probability of Single-Event Upsets (SEUs) for several orders of magnitude. In space applications it is necessary, therefore, to monitor the SEU rate in order to ensure timely detection of high radiation levels and efficient protection of radiation-sensitive circuits. This work proposes an approach combining the SEU monitoring and data storage functions in the same on-chip Static Random Access Memory (SRAM) module, with negligible cost and overheads compared to traditional stand-alone SEU monitors. Furthermore, it also enables the detection of permanent faults in SRAM. The proposed monitor is intended to be further integrated into a highly dependable and self-adaptive multiprocessing platform in which it will drive the selection of the multiprocessor operating modes. Thus, a dynamic trade-off between reliability, performance and power consumption in real-time can be achieved.