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Tianjin Zhao

dblp:391/8009 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2024
0000-0002-6492-040XORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
design for testability
0.812024
Component Dependencies Based Network-on-Chip Test · IEEE Trans. Computers 2024
Electronic design automation
hardware verification and test
0.812024
Component Dependencies Based Network-on-Chip Test · IEEE Trans. Computers 2024
Electronic design automation › hardware verification and test
test scheduling
0.812024
Component Dependencies Based Network-on-Chip Test · IEEE Trans. Computers 2024

Methods — techniques the papers use, named apart from their topics

test wrapper · 0.8test vector generation · 0.8partitioning · 0.8
YearPublicationVenuePosition
2024 Component Dependencies Based Network-on-Chip Test
abstract
On-line test of NoC is essential for its reliability. This paper proposed an integral test solution for on-line test of NoC to reduce the test cost and improve the reliability of NOC. The test solution includes a new partitioning method, as well as a test method and a test schedule which are based on the proposed partitioning method. The new partitioning method partitions the NoC into a new type of basis unit under test (UUT) named as interdependent components based unit under test (iDC-UUT), which applies component test methods. The iDC-UUT have very low level of functional interdependency and simple physical connection, which results in small test overhead and high test coverage. The proposed test method consists of DFT architecture, test wrapper and test vectors, which can speed-up the test procedure and further improve the test coverage. The proposed test schedule reduces the blockage probability of data packets during testing by increasing the degree of test disorder, so as to further reduce the test cost. Experimental results show that the proposed test solution reduces power and area by 12.7% and 22.7% over an existing test solution. The average latency is reduced by 22.6% to 38.4% over the existing test solution.
Letian Huang, Tianjin Zhao, Ziren Wang, Junkai Zhan, Junshi Wang, Xiaohang Wang 0001
IEEE Trans. Computers2