Demo Data from VLDB 2026 / reviewers in the wild / expert
Sota Kosugi
dblp:392/3339
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2024
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 61% Energy-efficient computing · 30% Memory systems · 9% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture › out-of-order execution
issue queue |
0.8 | 1 | 2024 | Localizing the Tag Comparisons in the Wakeup Logic to Reduce Energy Consumption of the Issue Queue · MICRO 2024 |
Energy-efficient computing › power management
processor power reduction |
0.8 | 1 | 2024 | Localizing the Tag Comparisons in the Wakeup Logic to Reduce Energy Consumption of the Issue Queue · MICRO 2024 |
Processor architecture and microarchitecture › instruction issue logic
wakeup logic |
0.8 | 1 | 2024 | Localizing the Tag Comparisons in the Wakeup Logic to Reduce Energy Consumption of the Issue Queue · MICRO 2024 |
Memory systems
content-addressable memory |
0.2 | 1 | 2024 | Localizing the Tag Comparisons in the Wakeup Logic to Reduce Energy Consumption of the Issue Queue · MICRO 2024 |
Methods — techniques the papers use, named apart from their topics
segmenting wakeup logic · 0.8partial tag comparison · 0.8
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | Localizing the Tag Comparisons in the Wakeup Logic to Reduce Energy Consumption of the Issue QueueabstractThere is a high demand to reduce the energy consumption of microprocessors. Among resources in a processor, the issue queue is one of the largest energy consumers, with much of the energy being consumed by the wakeup logic. The wakeup logic comprises the content-addressable memory, where tag comparisons are performed for all entries. Such global tag comparisons consume an appreciable amount of energy. This paper proposes a scheme called segmenting wakeup logic (SegWU), where the wakeup logic is segmented logically. An instruction is dispatched to an available entry in the segment selected based on the partial bits of the source tag values. At the wakeup time, a broadcast destination tag is compared only in the segment that corresponds to the partial bits of the destination tag value. Tag comparisons are not performed in the other segments. This localization of tag comparisons reduces the energy consumption. Our evaluation results for SPEC2017 benchmark programs show that SegWU reduces the number of tag comparisons by 90.3%. This lowers the IQ energy consumption, and the net reduction excluding the secondary effect (activity lowering of the front-end) and overhead is 3.0% in the base core energy consumption with no performance degradation. The overall energy reduction including the secondary effect is 6.9%. Kenichiro Mori, Sota Kosugi, Hiroto Yoshida, Hajime Shimada, Hideki Ando |
MICRO | 2 |