Tian-Ci Tian

dblp:395/7837 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2025
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 1 · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Emerging computing paradigms · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Emerging computing paradigms › quantum computer architecture
quantum compilation
0.912025
AI-Powered Algorithm-Centric Quantum Processor Topology Design · AAAI 2025
Emerging computing paradigms
quantum computer architecture
0.912025
AI-Powered Algorithm-Centric Quantum Processor Topology Design · AAAI 2025
Emerging computing paradigms › quantum computer architecture
qubit mapping
0.912025
AI-Powered Algorithm-Centric Quantum Processor Topology Design · AAAI 2025

Methods — techniques the papers use, named apart from their topics

reinforcement learning · 0.9
YearPublicationVenuePosition
2025 AI-Powered Algorithm-Centric Quantum Processor Topology Design
abstract
Quantum computing promises to revolutionize various fields, yet the execution of quantum programs necessitates an effective compilation process. This involves strategically mapping quantum circuits onto the physical qubits of a quantum processor. The qubits' arrangement, or topology, is pivotal to the circuit's performance, a factor that often defies traditional heuristic or manual optimization methods due to its complexity. In this study, we introduce a novel approach leveraging reinforcement learning to dynamically tailor qubit topologies to the unique specifications of individual quantum circuits, guiding algorithm-driven quantum processor topology design for reducing the depth of mapped circuit, which is particularly critical for the output accuracy on noisy quantum processors. Our method marks a significant departure from previous methods that have been constrained to mapping circuits onto a fixed processor topology. Experiments demonstrate that we have achieved notable enhancements in circuit performance, with a minimum of 20% reduction in circuit depth in 60% of the cases examined, and a maximum enhancement of up to 46%. Furthermore, the pronounced benefits of our approach in reducing circuit depth become increasingly evident as the scale of the quantum circuits increases, exhibiting the scalability of our method in terms of problem size. This work advances the co-design of quantum processor architecture and algorithm mapping, offering a promising avenue for future research and development in the field.
Xiao-Yue Xu, Tian-Ci Tian, Wei-You Liao, He-Liang Huang
AAAI4