Demo Data from VLDB 2026 / reviewers in the wild / expert
Kaibo Wu
dblp:396/6166
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2025
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 40% Emerging computing paradigms · 40% Hardware accelerators and domain-specific architectures · 20% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Emerging computing paradigms › neuromorphic computing
hyperdimensional computing |
0.9 | 1 | 2025 | A ReRAM-Based Processing-In-Memory Architecture for Hyperdimensional Computing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 |
Hardware accelerators and domain-specific architectures › neural network hardware › brain-inspired computing accelerator
hyperdimensional computing accelerator |
0.9 | 1 | 2025 | A ReRAM-Based Processing-In-Memory Architecture for Hyperdimensional Computing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 |
Emerging computing paradigms
neuromorphic computing |
0.9 | 1 | 2025 | A ReRAM-Based Processing-In-Memory Architecture for Hyperdimensional Computing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 |
Memory systems
processing-in-memory |
0.9 | 1 | 2025 | A ReRAM-Based Processing-In-Memory Architecture for Hyperdimensional Computing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 |
Memory systems › processing-in-memory
ReRAM-based processing-in-memory |
0.9 | 1 | 2025 | A ReRAM-Based Processing-In-Memory Architecture for Hyperdimensional Computing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 |
Methods — techniques the papers use, named apart from their topics
digital crossbar array · 0.9analog crossbar array · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | A ReRAM-Based Processing-In-Memory Architecture for Hyperdimensional ComputingabstractHyperdimensional computing (HDC) is a human brain-inspired computing paradigm that processes neural activity patterns with high dimensional vectors. Existing HDC accelerators usually utilize different hardware architectures to process encoding phases and comparison phases of HDC applications separately. They are unable to adapt to dynamic workloads for various datasets, resulting in resource underutilization. In this article, we propose a resistive random access memory (ReRAM)-based HDC accelerator called ReHDC for general HDC. We abstract the computing paradigms in encoding and comparison phases, and provide uniform primitive operators to efficiently process these two phases with the same hardware architecture. In the unified processing engine, ReHDC utilizes analog crossbar arrays to accelerate accumulation operations, and digital crossbar arrays to speed up high-dimensional element-wise operations (xor). Experimental results show that ReHDC can accelerate the HDC training by$69.4\times $and$1.93\times $, and can also improve the energy efficiency by$51.5\times $and$2.2\times $, compared with NVIDIA Tesla P100 GPU and the ReRAM-based HDC accelerator DUAL, respectively. Moreover, the performance speedup and energy efficiency for HDC inference are similar to that of HDC training. Cong Liu 0028, Kaibo Wu, Haikun Liu, Hai Jin 0001, Xiaofei Liao, Zhuohui Duan, Huize Li, Yu Zhang 0027, Jing Yang 0051 |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |