VLDB 2026 Research / reviewers in the wild / expert
Bjarne Wintermann
dblp:398/7192
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2025
0009-0000-0856-6250ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 50% High-performance computing · 25% Energy-efficient computing · 25% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Energy-efficient computing › energy-efficient machine learning
energy-efficient neural network inference |
0.9 | 1 | 2025 | Neural Network Inference in High-Performance Computing: Closing the Gap for FINN based Reconfigurable Accelerators · FPGA 2025 |
Hardware accelerators and domain-specific architectures › machine learning accelerator › neural network accelerator
FPGA-based neural network accelerator |
0.9 | 1 | 2025 | Neural Network Inference in High-Performance Computing: Closing the Gap for FINN based Reconfigurable Accelerators · FPGA 2025 |
Hardware accelerators and domain-specific architectures › machine learning accelerator › inference accelerator
neural network inference accelerator |
0.9 | 1 | 2025 | Neural Network Inference in High-Performance Computing: Closing the Gap for FINN based Reconfigurable Accelerators · FPGA 2025 |
Methods — techniques the papers use, named apart from their topics
quantization · 0.9dataflow-based inference · 0.9FINN framework · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Neural Network Inference in High-Performance Computing: Closing the Gap for FINN based Reconfigurable AcceleratorsabstractIn recent years, Neural Networks (NNs) have become one of the most prevailing topics in computers science, both in research and in industry. NNs are used for data analysis, natural language processing, autonomous driving and more. As such, NNs also see more application and use in High-Performance Computing (HPC). At the same time, energy efficiency has become an increasingly critical topic. NNs use large amounts of energy for operation, which in return results in large amounts of CO2 emissions. This work presents a comprehensive evaluation of current NN inference soft- and hardware configurations within High-Performance Computing (HPC) environments, with a focus on both performance metrics and energy consumption. NN quantization and accelerators such as FPGAs allow for an increased inference efficiency, both in terms of throughput and energy. Therefore, this work focuses on FINN, an efficient NN inference framework for FPGAs, highlighting its current lack of support for HPC systems. We provide an in-depth analysis of FINN in order to implement extensions to optimize the end-to-end execution for the usage in the HPC environment. We thoroughly evaluate the performance and energy efficiency gains using newly implemented optimizations and compare it against existing NN accelerators for HPC. With our extensions of FINN, we were able to achieve a 1847× higher throughput, while also decreasing the latency on average by 0.9978× and EDP by 0.9979× on an Alveo U55C FPGA. Data flow based NN inference accelerators on an FPGA should be used if the performance and energy footprint of the inference process is crucial, and the batch sizes are small to medium. For extremely large batch sizes and a very limited time for network-to-accelerator (less than a few days), using GPUs is still the way to go. Our results show that with the newly developed driver, we outperform a high-end Nvidia A100 GPU by up to 7.81x in throughput, while having a 0.87x lower latency and 0.88x lower energy delay product. Linus Jungemann, Bjarne Wintermann, Heinrich Riebler, Christian Plessl |
FPGA | 2 |