Scan is one of the representative Design for Testability (DFT) techniques designed to test sequential circuits. However, the additional hardware overhead and performance degradation caused by scan insertion can be unacceptable in specific designs. Partial scan has been applied as an alternative to the scan to balance these issues. However, previous cell selection algorithms accompany high computational complexity depending on the number of circuit components including flip-flops, and do not sufficiently consider the analysis of large-scale circuits. In this paper, a graph theory-based partial scan approach is proposed to effectively address the issues caused by scan insertion and reduce the load of structural analysis. The proposed algorithm partitions the circuit into multiple portions using graph clustering. Scan cells are selected from each subgraph to reduce sequential test generation complexity and improve testability. By partially analyzing the circuit, the proposed approach not only addresses the complexity problem of structural analysis in large-scale circuits but also can be generally applied regardless of circuit size or the number of components. The experimental results show that the proposed algorithm achieves significantly reduced processing time in seconds and reduces scan cells by approximately 11.47% with only 0.21% of test coverage loss on average compared to full scan design.

Partial scan design reduces the shortcomings of full-scan design while retaining its advantages by selectively converting flip-flops in a circuit. In many cases, specific flip-flops cannot be converted to scan cells due to design constraints. In this paper, a topology-based partial scan method is proposed to consider both stuck-at and delay testing. The need for delay testing is growing, yet conventional partial scan methods are ineffective for delay fault models. The proposed method should consider not only stuck-at fault models but also delay fault models. The proposed method introduces three processes. First, controllable flip-flops are selected for the shift operation without reducing circuit controllability. Second, observable flip-flops are selected for the capture operation without reducing circuit observability. Third, a logic topology-based algorithm is applied to ensure that both stuck-at and delay testing are considered in the selection process. As a result, the chosen flip-flops preserve controllability and observability close to that of a full-scan design, allowing the partial scan to remain effective for delay testing. Experimental results show that the proposed method achieves higher test coverage than the previous methods and enables efficient scan-based testing for both stuck-at and transition-delay fault models.

In the realm of automotive System-on-Chip (SoC), scan-based logic built-in self-test (LBIST) is commonly utilized for in-system testing, primarily for its cost-effectiveness. Nevertheless, this approach encounters challenges, particularly in attaining high-test coverage within constrained test times. The challenge intensifies when implementing low-power patterns, as it further complicates the achievement of adequate test coverage. To overcome these hurdles, this article introduces a novel testing methodology that enhances test coverage using low-toggled patterns. This method consists of two primary phases. Initially, it involves grouping and pairing scan cells (SCs), ensuring adjacent placement of paired cells. The following phase involves the generation of low-toggled patterns, tailored to the specific arrangement of SCs. To optimally detect as many previously undetected faults as possible, this method applies the low-power pattern selectively to particular scan groups. Furthermore, the scan group subjected to low-power patterns alternates after a certain number of patterns. Experimental results demonstrate the superiority of this proposed method in both fault detection and power reduction, in comparison to earlier methods.