VLDB 2026 Research / reviewers in the wild / expert
Luming Wang
dblp:40/10753
· DBLP profile ↗
6ranked-venue papers
2as first author
6since 2021 · last 2025
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 2 · 2 since 2021Systems, architecture and hardware · 2 · 1 first-author · 2 since 2021Applied, interdisciplinary, general and emerging computing · 2 · 1 first-author · 2 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 since 2021Human-computer interaction and ubiquitous computing · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Memory systems · 44% Processor architecture and microarchitecture · 34% Emerging computing paradigms · 17% | |
| Network and information security
1 paper |
Security and privacy of machine learning · 100% | |
| Artificial intelligence
1 paper |
Graph learning · 100% |
Topics — the 12 heaviest of 12, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Machine learning › Graph learning
graph neural network |
0.9 | 1 | 2025 | Clean-Label Graph Backdoor Attack in the Node Classification Task · AAAI 2025 |
Security and privacy of machine learning › adversarial attack
backdoor attack |
0.9 | 1 | 2025 | Clean-Label Graph Backdoor Attack in the Node Classification Task · AAAI 2025 |
Security and privacy of machine learning › adversarial attack › backdoor attack
graph backdoor attack |
0.9 | 1 | 2025 | Clean-Label Graph Backdoor Attack in the Node Classification Task · AAAI 2025 |
Memory systems › memory disaggregation
far memory |
0.8 | 1 | 2024 | Asynchronous Memory Access Unit: Exploiting Massive Parallelism for Far Memory Access · ACM Trans. Archit. Code Optim. 2024 |
Processor architecture and microarchitecture › load/store queue
load/store unit |
0.8 | 1 | 2024 | Asynchronous Memory Access Unit: Exploiting Massive Parallelism for Far Memory Access · ACM Trans. Archit. Code Optim. 2024 |
Memory systems › memory access optimization
memory-level parallelism |
0.8 | 1 | 2024 | Asynchronous Memory Access Unit: Exploiting Massive Parallelism for Far Memory Access · ACM Trans. Archit. Code Optim. 2024 |
Processor architecture and microarchitecture › out-of-order execution
out-of-order core |
0.8 | 1 | 2024 | Asynchronous Memory Access Unit: Exploiting Massive Parallelism for Far Memory Access · ACM Trans. Archit. Code Optim. 2024 |
Emerging computing paradigms
quantum computer architecture |
0.8 | 1 | 2024 | HF-VHF NEMS resonators enabled by 2D semiconductor ReSe2 · Sci. China Inf. Sci. 2024 |
Machine learning › Graph learning › graph neural network
node classification |
0.3 | 1 | 2025 | Clean-Label Graph Backdoor Attack in the Node Classification Task · AAAI 2025 |
Integrated circuit design
analog and mixed-signal circuits |
0.2 | 1 | 2024 | HF-VHF NEMS resonators enabled by 2D semiconductor ReSe2 · Sci. China Inf. Sci. 2024 |
Memory systems
cache |
0.2 | 1 | 2024 | Asynchronous Memory Access Unit: Exploiting Massive Parallelism for Far Memory Access · ACM Trans. Archit. Code Optim. 2024 |
Memory systems › on-chip memory
scratchpad memory |
0.2 | 1 | 2024 | Asynchronous Memory Access Unit: Exploiting Massive Parallelism for Far Memory Access · ACM Trans. Archit. Code Optim. 2024 |
Methods — techniques the papers use, named apart from their topics
uncertainty-based node selection · 1.7feature triggers · 1.7clean-label poisoning · 1.7cycle-accurate simulation · 0.8coroutine-based programming · 0.8
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Clean-Label Graph Backdoor Attack in the Node Classification TaskabstractGraph neural networks (GNNs) have achieved impressive results in various graph learning tasks. Backdoor attacks pose a significant threat to GNNs, with a focus on dirty-label attacks. However, these attacks often necessitate the inclusion of blatantly incorrect inputs into the training set, rendering them easily detectable through simple filtering. In response to this challenge, we introduce Clean-Label Graph Backdoor Attack (CGBA). The majority of features in the generated poisoned nodes align with their true labels, significantly enhancing the difficulty of detecting the attack. Firstly, leveraging the uncertainty inherent in the GNNs, we develop a low-budget strategy for selecting poisoned nodes. This approach focuses on nodes in the target class with uncertain and low-degree classifications, allowing for efficient attacks within a limited budget while mitigating the impact on other clean nodes. Secondly, we present an innovative strategy for generating feature triggers. By boosting the confidence of poisoned samples in the target class, this tactic establishes a robust association between the trigger and the target class, even without modifying the labels of poisoned nodes. Additionally, we incorporate two constraints to reduce disruption to the graph structure. In conclusion, comprehensive experimental results unequivocally showcase CGBA's exceptional attack performance across three benchmark datasets and four GNNs models. Notably, the attack targeting the GraphSAGE model attains a 100% success rate, accompanied by a marginal benign accuracy drop of no more than 0.5%. Hui Xia 0001, Xiangwei Zhao, Rui Zhang 0050, Luming Wang |
AAAI | 5 |
| 2025 | EgoEvGesture: Gesture Recognition Based on Egocentric Event CameraabstractEgocentric gesture recognition is a pivotal technology for enhancing natural human-computer interaction, yet traditional RGB-based solutions suffer from motion blur and illumination variations in dynamic scenarios. While event cameras show distinct advantages in handling high dynamic range with ultra-low power consumption, existing RGB-based architectures face inherent limitations in processing asynchronous event streams due to their synchronous frame-based nature. Moreover, from an egocentric perspective, event cameras record data that includes events generated by both head movements and hand gestures, thereby increasing the complexity of gesture recognition. To address this, we propose a novel network architecture specifically designed for event data processing, incorporating (1) a lightweight CNN with asymmetric depthwise convolutions to reduce parameters while preserving spatiotemporal features, (2) a plug-and-play state-space model as context block that decouples head movement noise from gesture dynamics, and (3) a parameter-free Bins-Temporal Shift Module (BTSM) that shifts features along bins and temporal dimensions to fuse sparse events efficiently. We further establish the EgoEvGesture dataset, the first large-scale dataset for egocentric gesture recognition using event cameras. Experimental results demonstrate that our method achieves 62.7% accuracy tested on unseen subjects with only 7M parameters, 3.1% higher than state-of-the-art approaches. Notable misclassifications in freestyle motions stem from high interpersonal variability and unseen test patterns differing from training data. Moreover, our approach achieved a remarkable accuracy of 97.0% on the DVS128 Gesture, demonstrating the effectiveness and generalization capability of our method on public datasets. The dataset and models are made available at https://github.com/3190105222/EgoEv_Gesture. Luming Wang, Hao Shi 0004, Xiaoting Yin, Kailun Yang 0001, Kaiwei Wang |
SMC | 1 |
| 2024 | HF-VHF NEMS resonators enabled by 2D semiconductor ReSe2
Ziluo Su, Shuang Cai, Yalan Wang, Luming Wang, Jiaze Qin, Jiankai Zhu, Juan Xia, Zenghui Wang 0006 |
Sci. China Inf. Sci. | 5 |
| 2024 | Intelligent identification of girth welds defects in pipelines using neural networks with attention modules
Lushuai Xu, Shaohua Dong, Haotian Wei, Donghua Peng, Weichao Qian, Qingying Ren, Luming Wang, Yundong Ma |
Eng. Appl. Artif. Intell. | 7 |
| 2024 | Asynchronous Memory Access Unit: Exploiting Massive Parallelism for Far Memory AccessabstractThe growing memory demands of modern applications have driven the adoption of far memory technologies in data centers to provide cost-effective, high-capacity memory solutions. However, far memory presents new performance challenges because its access latencies are significantly longer and more variable than local DRAM. For applications to achieve acceptable performance on far memory, a high degree of memory-level parallelism (MLP) is needed to tolerate the long access latency. While modern out-of-order processors are capable of exploiting a certain degree of MLP, they are constrained by resource limitations and hardware complexity. The key obstacle is the synchronous memory access semantics of traditional load/store instructions, which occupy critical hardware resources for a long time. The longer far memory latencies exacerbate this limitation. This article proposes a set of Asynchronous Memory Access Instructions (AMI) and its supporting function unit, Asynchronous Memory Access Unit (AMU), inside contemporary Out-of-Order Core. AMI separates memory request issuing from response handling to reduce resource occupation. Additionally, AMU architecture supports up to several hundreds of asynchronous memory requests through re-purposing a portion of L2 Cache as scratchpad memory (SPM) to provide sufficient temporal storage. Together with a coroutine-based programming framework, this scheme can achieve significantly higher MLP for hiding far memory latencies. Evaluation with a cycle-accurate simulation shows AMI achieves 2.42× speedup on average for memory-bound benchmarks with 1μs additional far memory latency. Over 130 outstanding requests are supported with 26.86× speedup for GUPS (random access) with 5 μs latency. These demonstrate how the techniques tackle far memory performance impacts through explicit MLP expression and latency adaptation. Luming Wang, Xu Zhang 0033, Songyue Wang, Zhuolun Jiang, Tianyue Lu, Mingyu Chen 0001, Siwei Luo, Keji Huang |
ACM Trans. Archit. Code Optim. | 1 |
| 2023 | Vision-Based Real-Time Tracking of Surgical Instruments in Robot-Assisted Laparoscopic SurgeryabstractRobot-assist laparoscopic surgery has been widely acknowledged in the minimally invasive surgery for its capability of operating within limited space and its robustness. Particularly, the vision-guided camera-holder system is suggested worldwide for it could track the instruments autonomously without additional equipment and its low cost, in which computer vision contributes a lot to the recognition and localization of the surgical instruments. This paper proposes vision-based real-time tracking of three basic surgical instruments in laparoscopic surgery. Two algorithms in computer vision are compared for instruments detection - Template Matching and Deep Learning, and the real-time tracking is completed based on the detection. Optimizations are made for both of algorithms. For Template Matching, three methods to enhance efficiency are applied. For Deep Learning, different loss functions and Attention Mechanisms are introduced and compared. Models are evaluated by the metrics of Precision, Recall and Detecting Time. The results reveal that despite the high precision of 0.83, the detection time of Template Matching reaches above 5000 ms, which is too slow to meet the real-time requirements in the surgery, while YOLOv5 models with CIoU and SENet performs best overall with the precision of 0.98 and the detection time of around 20 ms. Wenhan Lin, Jinze Shi, Honghai Ma, Luming Wang, Chunlin Zhou |
IECON | 4 |