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Binh Vien Dao

dblp:40/1267 · DBLP profile ↗
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6ranked-venue papers
3as first author
0since 2021 · last 2000
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 6 · 3 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
5 papers
Interconnection networks and networks-on-chip · 70% Hardware reliability and fault tolerance · 12% Distributed systems · 7%

Topics — the 16 heaviest of 17, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › routing algorithms
fault-tolerant routing
0.132000
Software-Based Rerouting for Fault-Tolerant Pipelined Communication · IEEE Trans. Parallel Distributed Syst. 2000
Dynamically Configurable Message Flow Control for Fault-Tolerant Routing · IEEE Trans. Parallel Distributed Syst. 1999
Configurable Flow Control Mechanisms for Fault-Tolerant Routing · ISCA 1995
Interconnection networks and networks-on-chip
router architecture
0.021997
Architectural Support for Reducing Communication Overhead in Multiprocessor Interconnection Networks · HPCA 1997
Configurable Flow Control Mechanisms for Fault-Tolerant Routing · ISCA 1995
Interconnection networks and networks-on-chip
communication locality
0.011997
Architectural Support for Reducing Communication Overhead in Multiprocessor Interconnection Networks · HPCA 1997
Distributed systems › communication optimization
communication overhead reduction
0.011997
Architectural Support for Reducing Communication Overhead in Multiprocessor Interconnection Networks · HPCA 1997
Interconnection networks and networks-on-chip
network interface
0.011997
Architectural Support for Reducing Communication Overhead in Multiprocessor Interconnection Networks · HPCA 1997
Interconnection networks and networks-on-chip › routing algorithms
deadlock-free routing
0.011996
Distributed Deadlock-Free Routing in Faulty, Pipelined, Direct Interconnection Networks · IEEE Trans. Computers 1996
Hardware reliability and fault tolerance › network fault tolerance
fault-tolerant interconnection network
0.011996
Distributed Deadlock-Free Routing in Faulty, Pipelined, Direct Interconnection Networks · IEEE Trans. Computers 1996
Interconnection networks and networks-on-chip
flow control
0.011995
Configurable Flow Control Mechanisms for Fault-Tolerant Routing · ISCA 1995
Electronic design automation › physical design
routing
0.011995
Configurable Flow Control Mechanisms for Fault-Tolerant Routing · ISCA 1995
Hardware reliability and fault tolerance › network fault tolerance
fault-tolerant multiprocessor networks
0.012000
Software-Based Rerouting for Fault-Tolerant Pipelined Communication · IEEE Trans. Parallel Distributed Syst. 2000
Interconnection networks and networks-on-chip › routing algorithms
wormhole routing
0.012000
Software-Based Rerouting for Fault-Tolerant Pipelined Communication · IEEE Trans. Parallel Distributed Syst. 2000
Cloud and datacenter computing › resource management › shared resource management
deadlock avoidance
0.011999
Dynamically Configurable Message Flow Control for Fault-Tolerant Routing · IEEE Trans. Parallel Distributed Syst. 1999
Hardware reliability and fault tolerance
network fault tolerance
0.011999
Dynamically Configurable Message Flow Control for Fault-Tolerant Routing · IEEE Trans. Parallel Distributed Syst. 1999
Interconnection networks and networks-on-chip
cluster interconnect
0.011997
Architectural Support for Reducing Communication Overhead in Multiprocessor Interconnection Networks · HPCA 1997
Parallel and multicore computing › parallel programming models
message passing
0.011997
Architectural Support for Reducing Communication Overhead in Multiprocessor Interconnection Networks · HPCA 1997
Interconnection networks and networks-on-chip › flow control
virtual channel flow control
0.011996
Distributed Deadlock-Free Routing in Faulty, Pipelined, Direct Interconnection Networks · IEEE Trans. Computers 1996

Methods — techniques the papers use, named apart from their topics

simulation · 0.1wormhole switching · 0.0pipelined circuit switching · 0.0trace-driven simulation · 0.0flit-level simulation · 0.0
YearPublicationVenuePosition
2000 Software-Based Rerouting for Fault-Tolerant Pipelined Communication
abstract
This paper presents a software-based approach to fault-tolerant routing in networks using wormhole or virtual cut-through switching. When a message encounters a faulty output link, it is removed from the network by the local router and delivered to the messaging layer of the local node's operating system. The message passing software can reroute this message, possibly along nonminimal paths. Alternatively, the message may be addressed to an intermediate node, which will forward the message to the destination. A message may encounter multiple faults and pass through multiple intermediate nodes. The proposed techniques are applicable to both obliviously and adaptively routed networks. The techniques are specifically targeted toward commercial multiprocessors where the mean time to repair (MTTR) is much smaller than the mean time between router failures (MTBF), i.e., it is sufficient to tolerate a maximum of three failures. This paper presents requirements for buffer management, deadlock freedom, and livelock freedom. Simulation results are presented to evaluate the degradation in latency and throughput as a function of the number and distribution of faults. There are several advantages of such an approach. Router designs are minimally impacted, and thus remain compact and fast. Only messages that encounter faulty components are affected, while the machine is ensured of continued operation until the faulty components can be replaced. The technique leverages existing network technology, and the concepts are portable across evolving switch and router designs. Therefore, we feel that the technique is a good candidate for incorporation into the next generation of multiprocessor networks.
Young-Joo Suh, Binh Vien Dao, José Duato, Sudhakar Yalamanchili
IEEE Trans. Parallel Distributed Syst.2
1999 Dynamically Configurable Message Flow Control for Fault-Tolerant Routing
abstract
Fault-tolerant routing protocols in modern interconnection networks rely heavily on the network flow control mechanisms used. Optimistic flow control mechanisms, such as wormhole switching (WS), realize very good performance, but are prone to deadlock in the presence of faults. Conservative flow control mechanisms, such as pipelined circuit switching (PCS), ensure the existence of a path to the destination prior to message transmission, achieving reliable transmission at the expense of performance. This paper proposes a general class of flow control mechanisms that can be dynamically configured to trade-off reliability and performance. Routing protocols can then be designed such that, in the vicinity of faults, protocols use a more conservative flow control mechanism, while the majority of messages that traverse fault-free portions of the network utilize a WS like flow control to maximize performance. We refer to such protocols as two-phase protocols. This ability provides new avenues for optimizing message passing performance in the presence of faults. A fully adaptive two-phase protocol is proposed, and compared via simulation to those based on WS and PCS. The architecture of a network router supporting configurable flow control is also described.
Binh Vien Dao, José Duato, Sudhakar Yalamanchili
IEEE Trans. Parallel Distributed Syst.1
1997 Architectural Support for Reducing Communication Overhead in Multiprocessor Interconnection Networks
abstract
Modern multicomputer interconnection networks offer the delivery of messages with very low latency. However the message in-flight time is only a small portion of the total time that is required to send a message from source to destination. For fine to medium grained message sizes, the majority of time is spent in overheads for setting up and managing message transmission. It is often possible for compilers/programmers to separate inter-processor communication traffic into messages that exhibit communication locality and messages that do not. This paper proposes architectural modifications to network interfaces and routers to enable compilers/programmers to exploit known locality properties of programs in reducing the fixed overhead of transmission. These techniques work well on traffic exhibiting communication locality without unduly penalizing "ordinary" message traffic. The proposed techniques are evaluated using communication traces from 5 application program kernels. Significant reductions in average message latency are possible, and we argue that the approach can be used in the next generation of cluster interconnects.
Binh Vien Dao, Sudhakar Yalamanchili, José Duato
HPCA1
1996 Distributed Deadlock-Free Routing in Faulty, Pipelined, Direct Interconnection Networks
abstract
This paper focuses on designing high performance pipelined networks that can operate in the presence of dynamic component failures. A general, rigorous framework for deadlock-free communication in faulty, pipelined networks is developed. A mechanism is also proposed for recovering from dynamic link and node failures. The recovery mechanism (1) is fully distributed, (2) does not require timeouts, (3) prevents fault-induced deadlock, and (4) is integrated into the virtual channel flow control mechanisms. This recovery mechanism is used to develop a new pipelined communication mechanism-acknowledged pipelined circuit-switching (APCS). This mechanism supports existing routing protocols that can tolerate a maximal number of static link failures, i.e., one less than the number of ports on a node. An implementation of a novel router architecture is described and the results of detailed flit level simulations are presented. Finally, the proposed recovery mechanism is shown to be applicable to existing adaptive wormhole routing protocols which are prone to deadlock in the presence of dynamic faults.
Patrick T. Gaughan, Binh Vien Dao, Sudhakar Yalamanchili, David E. Schimmel
IEEE Trans. Computers2
1995 Software Based Fault-Tolerant Oblivious Routing in Pipelined Networks
Young-Joo Suh, Binh Vien Dao, José Duato, Sudhakar Yalamanchili
ICPP (1)2
1995 Configurable Flow Control Mechanisms for Fault-Tolerant Routing
abstract
Fault-tolerant routing protocols in modern interconnection networks rely heavily on the network flow control mechanisms used. Optimistic flow control mechanisms such as wormhole routing (WR) realize very good performance, but are prone to deadlock in the presence of faults. Conservative flow control mechanisms such as pipelined circuit switching (PCS) insures existence of a path to the destination prior to message transmission, but incurs increased overhead. Existing fault-tolerant routing protocols are designed with one or the other, and must accommodate their associated constraints. This paper proposes the use of configurable flow control mechanisms. Routing protocols can then be designed such that in the vicinity of faults, protocols use a more conservative flow control mechanism, while the majority of messages that traverse fault-free portions of the network utilize a WR like flow control to maximize performance. Such protocols are referred to as two-phase protocols, where routing decisions are provided some control over the operation of the virtual channels. This ability provides new avenues for optimizing message passing performance in the presence of faults. A fully adaptive two-phase protocol is proposed and compared via simulation to those based on WR and PCS. The architecture of a network router supporting configurable flow control is described, and the paper concludes with avenues for future research.
Binh Vien Dao, José Duato, Sudhakar Yalamanchili
ISCA1