The adoption of decentralized architectures for health data management offers benefits including patient data sovereignty and elimination of single points of failure, but introduces questions about network overhead compared to traditional centralized systems. This paper presents a network overhead analysis comparing Firebase Real-Time Database with IPFS-based storage via Pinata for mobile health data transmission. We implemented an Android application that collects physiological data from wearable devices and transmits this information to both backends using REST APIs. Our experimental evaluation across eight transmission scales reveals that Firebase demonstrates lower fixed overhead and latency for small payloads, while Pinata exhibits superior scaling characteristics for larger data volumes. A crossover point occurs around 50 records per payload, beyond which the decentralized architecture transmits less total data than the centralized alternative. The results indicate that neither architecture maintains uniform efficiency across all operational scales, with architectural choice depending on expected transaction patterns in the deployment context.

Current health data management relies on centralized architectures that create a single point of failure, limit patient autonomy, and increase vulnerability to data breaches and vendor lock-in. This paper presents a decentralized approach to continuous health monitoring through the integration of wearable devices and distributed file systems. We implemented an Android application that collects physiological data and contextual information from a wearable device, storing it on the IPFS via Pinata API. Additionally, we propose a blockchain architecture for role-based access control. Performance evaluation comparing our IPFS-based implementation against Firebase Real-Time database reveals that the resource requirements remain negligible for modern smartphones while achieving significant benefits, including no single point of failure, enhanced data portability, and patient data sovereignty. The results demonstrate that decentralized health data management is technically feasible on mobile devices, offering an alternative approach to traditional centralized health data architectures.

This work documents the recent rise in popularity of messaging bots: chatterbot-like agents with simple, textual interfaces that allow users to access information, make use of services, or provide entertainment through online messaging platforms. Conversational interfaces have been often studied in their many facets, including natural language processing, artificial intelligence, human-computer interaction, and usability. In this work we analyze the recent trends in chatterbots and provide a survey of major messaging platforms, reviewing their support for bots and their distinguishing features. We then argue for what we call "Botplication", a bot interface paradigm that makes use of context, history, and structured conversation elements for input and output in order to provide a conversational user experience while overcoming the limitations of text-only interfaces.

This work is part of a project, SmartRoadSense, aimed to estimate the quality of the road surface exploiting the sensors of a mobile device anchored to the car cabin. Using the data of the triaxial accelerometer and the vehicle speed provided by GPS system, it has been shown that an estimate of the quality of road surface can be obtained. In order to improve this estimate, the paper studies the dependence of the mobile device vertical acceleration on the vehicle speed. Using a theoretical model and experimental results, it is shown how the average power of the vertical acceleration and the road roughness index estimated by SmartRoadSense are related to speed.

No abstract available.

Out-of-band signaling provides a valuable support to the management of wireless sensor networks. Among other signals, sound has a propagation speed in air which is fast enough to be neglected in typical sensor network applications, and slow enough to be measured by means of low-cost embedded systems. An ultrasonic triggering mechanism has been recently developed for VirtualSense, an ultra-low-power sensor node featuring a Java runtime environment. Ultrasonic triggers provide on-demand wakeup capabilities that can be exploited by routing nodes to be switched on whenever there is a packet to be routed towards the sink, while spending all the idle time in an ultra low power inactive state where even the radio module is turned off. In addition, the same hardware components can be used to perform pairwise distance measurements that can be exploited for localization. In this demonstration we show the possible use of VirtualSense ultrasonic wake-up modules as distance estimators.

The widespread diffusion of wireless sensor networks and wearable devices, together with the emergence of energy harvesting techniques, has motivated the development of ultra-low-power micro controller units (MCUs) which are highly energy efficient in active mode and provide a wide range of sleep states to be possibly exploited to save power during idle periods. In spite of their energy efficiency, state-of-the-art MCUs exhibit 16-bit RISC architectures clocked at up to tens of MHz and equipped with at least 16kbytes of main memory and 64kbytes of flash. This makes them suitable to run a virtual machine, bringing the benefits of a virtual runtime environment to power-constrained embedded systems. Virtual machines, however, impair the effectiveness of dynamic power management since they are seen as always-active processes by the scheduler of the operating system. This paper presents a power-manageable open-source embedded virtual environment based on a modified version of the Darjeeling VM running on top of Contiki OS. The proposed architecture has been implemented and tested on Texas Instruments' MSP430 MCUs which have been used as a testbed for the characterization of the power consumption and transitions cost of each power state.

Cooperation incentives are essential in user-centric networks to motivate users to share services and resources (including bandwidth, computational power, and storage space) and to avoid selfish nodes to hinder the functioning of the entire system. Virtual currency and reputation mechanisms are commonly adopted in online communities to boost participation, but their joint application has not been deeply explored, especially in the context of wireless communities, where not only the services, but even the enabling infrastructure is opportunistically built by community members. This paper investigates the combined use of virtual currency and reputation-based incentives in the specific context of a community of users with Wi-Fi enabled devices capable of establishing ad-hoc connections.

Internet traffic trends and forecasts clearly show that audio-video streaming is a killer application for next generation networks. Providing multicast support within operators' managed networks is mandatory to sustain the exponential growth of demand for multimedia contents without saturating the bandwidth available in core, backhauling, and access infrastructures. This work presents an experimental setup, built on top of an open source platform called openBOXware, which enables protected delivery of multimedia contents over unprotected multicast IP networks.

Energy harvesting technologies make it possible to exploit environmental power to realize autonomous wireless sensor networks with unlimited lifetime. However, the actual autonomy of a wireless network depends on the energetic sustainability of its workload that depends, on its turn, on the algorithms adopted to route packets from the sensor nodes to the sink. A theoretical framework for assessing and optimizing the energetic sustainability of routing algorithms has been recently proposed. In this paper we discuss the actual applicability of optimal energetically sustainable routing algorithms and the issues raised by non-stationary environmental conditions. Furthermore, we present a distributed algorithm, running on sensor nodes, that is able to re-compute optimal routing tables on the field in order to adapt to the actual distribution of environmental power.

Virtual memory is considered to be an unlimited resource in desktop or notebook computers with high storage capabilities. However, in wireless mobile devices, like palmtops and personal digital assistants (PDAs), storage memory is limited or absent due to weight, size, and power constraints, so that swapping over remote memory devices can be considered as a viable alternative. However, power-hungry wireless network interface cards (WNICs) may limit the battery lifetime and application performance if not efficiently exploited. In this paper, we study performance and energy of network swapping in comparison with swapping on local microdrives and flash memories. We report the results of extensive experiments conducted on different WNICs and local swapping devices, using both synthetic and natural benchmarks. Our study points out that remote swapping over power-manageable WNICs can be more efficient than local swapping, especially in bursty workload conditions. Such conditions can be forced where possible by reshaping swapping requests to increase energy efficiency and performance.

MOTIVATION: Matching a biological sequence against a probabilistic pattern (or profile) is a common task in computational biology. A probabilistic profile, represented as a scoring matrix, is more suitable than a deterministic pattern to retain the peculiarities of a given segment of a family of biological sequences. Brute-force algorithms take O(NP) to match a sequence of N characters against a profile of length P << N. RESULTS: In this work, we exploit string compression techniques to speedup brute-force profile matching. We present two algorithms, based on run-length and LZ78 encodings, that reduce computational complexity by the compression factor of the encoding.

Virtual memory is considered to be an unlimited resource in desktop or notebook computers with high storage memory capabilities. However, in wireless mobile devices like palmtops and personal digital assistants (PDA), storage memory is limited or absent due to weight, size and power constraints. As a consequence, swapping over remote memory devices can be considered as a viable alternative. Nevertheless, power hungry wireless network interface cards (WNIC) may limit the battery lifetime and application performance if not efficiently exploited. In this work we explore performance and energy of network swapping in comparison with swapping on local micro-drives and flash memories. Our study points out that remote swapping over power-manageable WNICs can be more efficient than local swapping and that both energy and performance can be optimized through power-aware reshaping of data requests. Experimental results show that our optimization technique can save up to 60% of communication energy while improving performance.

In this paper we provide an incremental methodology to assess the effect of the introduction of a dynamic power manager in a mobile embedded computing device. The methodology consists of two phases. In the first phase, we verify whether the introduction of the dynamic power manager alters the functionality of the system. We show that this can be accomplished by employing standard techniques based on equivalence checking for noninterference analysis. In the second phase, we quantify the effectiveness of the introduction of the dynamic power manager in terms of power consumption and overall system efficiency. This is carried out by enriching the functional model of the system with information about the performance aspects of the system, and by comparing the values of the power consumption and the overall system efficiency obtained from the solution of the performance model with and without dynamic power manager. To this purpose, first we employ a more abstract performance model based on the Markovian assumption, then we use a more realistic performance model - to be validated against the Markovian one - where general probability distributions are considered. The methodology is illustrated by means of its application to the study of a remote procedure call mechanism - through which a battery-powered device is used by some application requesting information - and of a streaming video service - which is accessed by a mobile client equipped with a power-manageable network interface card.

Summary form only given. With the diffusion of Java in advanced multimedia mobile devices, there is a growing need for speeding up the execution of Java bytecode beyond the limits of traditional interpreters and just-in-time compilers. In this area, Java coprocessors are viewed as a promising technology, which marries the flexibility of a general-purpose microprocessor to run legacy code and lightweight Java methods, with the high performance of a specialized execution engine on speed-critical bytecode. We propose and analyze a microprocessor with FPGA coprocessor architecture with efficient shared-memory communication support. Furthermore, we describe a complete run-time environment that supports dynamic migration of Java methods to the coprocessor, and we quantitatively analyze speedups achievable under a number of system configurations using an accurate complete-system simulator.

One of the major concern for 802.11b wireless local area network is energy efficiency. In fact, mobile devices spend a large amount of power on their radio interface for accessing multimedia services such as audio and video streaming.In this work we address the problem of energy-aware scheduling of treaming data provided by a single server to multiple clients. We propose both open-loop and closed-loop strategies that exploit application level information to perform energy-effiocient traffic reshaping.We evaluate the effectiveness of the proposed trategies by means of accurate power/performance imulations performed on top of Mathworks' Simulink. System component are modeled as generalized semi-markov processes (GSMPs) and characterized by mean of real-world measurements. In particular, the timing and power behavior of wireless network interface cards is accurately captured in order to evaluate the impact of power management strategies on a wireless 802.11b link. Experimental result how that up to 75%of the communication energy can be aved by mean of power-aware traffic scheduling with negligible user-perceived performance degradation.

Dynamic power management encompasses several techniques for reducing energy dissipation in electronic systems by selective slowdown or shutdown of components. We present a theoretical framework for explaining and classifying different approaches to power management. Within this framework, we model power-manageable components, workloads, and controllers as discrete-event systems (DESs). The structure of these DESs is specified in terms of physical states (representing operation modes) and events (triggering state transitions), while system behavior is specified in terms of next-event and next-state functions. In particular, nondeterministic next-event and next-state functions are modeled by conditional probability distributions, according to generalized semi-Markov processes (GSMPs). The modeling framework provides a general denotational model for system specification and a rigorous execution semantics that enables event-driven simulation. We introduce a modeling framework, built on top of MathWork's Simulink, supporting the specification and execution of our model. In particular, we present templates for the Simulink simulator to execute GSMP models, and we describe how to use such templates for specifying, analyzing, and optimizing dynamic power-managed systems. Finally, we demonstrate the expressive power and versatility of the proposed approach by using the modeling framework and the simulator for the analysis of representative real-life case studies, including the Intel Xscale processor architecture, a multitasking real-time system, and a sensor network.

We use a case study (namely, the interactive continuous browsing of large geographical maps provided by a remote GIS server) to evaluate the suitability of state-of-the-art personal digital assistants (PDA) with an embedded Java virtual machine to be used as mobile access points of continuous graphical contents provided on demand by a remote server.

Dynamic power management (DPM) is a design methodology aimed at reducing power consumption of electronic systems by performing selective shutdown of idle system resources. The effectiveness of a power management scheme depends critically on accurate modeling of service requests and on computation of the control policy. In this work, we present an online adaptive DPM scheme for systems that can be modeled as finite-state Markov chains. Online adaptation is required to deal with initially unknown or nonstationary workloads, which are very common in real-life systems. Our approach moves from exact policy optimization techniques in a known and stationary stochastic environment and extends optimum stationary control policies to handle the unknown and nonstationary stochastic environment for practical applications. We introduce two workload learning techniques based on sliding windows and study their properties. Furthermore, a two-dimensional interpolation technique is introduced to obtain adaptive policies from a precomputed look-up table of optimum stationary policies. The effectiveness of our approach is demonstrated by a complete DPM implementation on a laptop computer with a power-manageable hard disk that compares very favorably with existing DPM schemes.

The capability of performing semi-automated design space exploration is the main advantage of high-level synthesis with respect to RTL design. However, design space exploration performed during high-level synthesis is limited in scope, since it provides promising solutions that represent good starting points for subsequent optimizations, but it provides no insight about the overall structure of the design space. In this work we propose unsupervised Monte-Carlo design exploration and statistical characterization to capture the key features of the design space. Our analysis provides insight on how various solutions are distributed over the entire design space. In addition, we apply extreme value theory [11] to extrapolate achievable bounds from the sampling points.

Article Share on Encodings for high-performance for energy-efficient signaling Author: Alessandro Bogliolo DIF, University of Ferrara, 44100 Ferrara, Italy DIF, University of Ferrara, 44100 Ferrara, ItalyView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001Pages 170–175https://doi.org/10.1145/383082.383126Published:06 August 2001Publication History 4citation134DownloadsMetricsTotal Citations4Total Downloads134Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Publisher SiteGet Access

We propose a new power macromodel for usage in the context of register-transfer level (RTL) power estimation. The model is suitable for reconfigurable, synthesizable, soft macros because it is parameterized with respect to the input data size (i.e., bit width) and can also be automatically scaled with respect to different technology libraries and/or synthesis options. The power model is precharacterized once and for all for each soft macro and then adapted to each specific instance by means of a single additional experiment to be performed by the end user. No intellectual-property disclosure is required for model scaling. The proposed model is derived from empirical analysis of the sensitivity of power consumption on input statistics, input data size, and technology. The experiments prove that with limited approximation, it is possible to decouple the effects on power of these three factors. The proposed solution is innovative since no previous macromodel supports automatic technology scaling and yields average estimation errors around 10%.

Design methodologies based on reuse of intellectual property (IP) components critically depend on techniques to protect IP ownership. IP protection is particularly challenging for hardware/software systems, where an IP core runs embedded software: both the software and the core are valuable IP that must be protected.

Fault simulation and testability analysis are major concerns in design flows employing intellectual-property (IP) protected virtual components. In this paper we propose a paradigm for the fault simulation of IP-based designs that enables testability analysis without requiring IP disclosure, implemented within the JavaCAD framework for distributed design. As a proof of concept, stuck-at fault simulation has been performed for combinational circuits containing virtual components.

Power consumption of the controller of an RTL design, though typically smaller than that of the datapath, cannot be neglected. Controller power modeling is a more challenging task than that of datapath modules, because the controller is usually specified in an abstract fashion that has no structural relationship with its final implementation. This paper presents an extensive experimental study on pre-state assignment power models. Starting from a large set of controllers, we study the relation between power and static parameters, such as number of inputs and outputs, as well as dynamic parameters, such as input and output switching activity. We then quantify the loss of accuracy caused by the high level of abstraction of the models, and we show how previously published results, obtained under favorable experimental conditions, have underestimated model inaccuracy. Finally, we perform extensive exploration on a large number of alternative macro-model structures, and we select an optimal model equation.

Register-transfer level (RTL) power estimation is a key feature for synthesis-based design flows. The main challenge in establishing a sound RTL power estimation methodology is the construction of accurate, yet efficient, models of the power dissipation of functional macros. Such models should be automatically built, and should produce reliable average power estimates. In this paper we propose a general methodology for building and tuning RTL power models. We address both hard macros (presynthesized functional blocks)and soft macros (functional units for which only a synthesizable HDL description is provided). We exploit linear regression and its nonparametric extensions to express the dependency of power dissipation on input and output activity. Bottom-up off-line characterization of regression-based power macromodels is discussed in detail. Moreover, we introduce a low overhead on-line characterization method for enhancing the accuracy of off-line characterization.

Dynamic power management (DPM) is a design methodology for dynamically reconfiguring systems to provide the requested services and performance levels with a minimum number of active components or a minimum load on such components. DPM encompasses a set of techniques that achieves energy-efficient computation by selectively turning off (or reducing the performance of) system components when they are idle (or partially unexploited). In this paper, we survey several approaches to system-level dynamic power management. We first describe how systems employ power-manageable components and how the use of dynamic reconfiguration can impact the overall power consumption. We then analyze DPM implementation issues in electronic systems, and we survey recent initiatives in standardizing the hardware/software interface to enable software-controlled power management of hardware components.

The reliability of a fault-tolerant circuit may be drastically impaired by the presence of maskable faults that never affect its functionality. Design for testability (DFT) techniques have to be applied to make maskable faults detectable. During the testing phase, traditional DFT schemes inhibit fault masking and/or activate additional observation/control paths through the circuit. Such schemes, however, do not enable on-line testing and cannot be applied to multilevel fault-tolerant circuits, where fault-masking is repeatedly performed inside the circuit. We propose a new approach to the design of testable fault-tolerant CMOS circuits that overcomes both limitations. Our approach is based on the use of I/sub DDQ/-checkable voters (ICVs) that enable a complete test of maskable faults of any multiplicity during normal operations.

One key issue in design flows based on reuse of third-party intellectual property (IP) components is the need to estimate the impact of component instantiation within complex designs. In this paper we introduce JavaCAD, an Internet-based EDA tool built on a secure client-server architecture that enables designers to perform simulation and cost estimation of circuits containing IP components without actually purchasing them. At the same time, the tool ensures intellectual property protection for the vendors of IP components, and for the IP-users as well. Moreover, JavaCAD supports negotiation of the amount of information and the accuracy of cost estimates, thereby providing seamless transition between IP evaluation and purchase.

Dynamic power management is a design methodology aiming at reducing power consumption of electronic systems, by performing selective shutdown of the idle system resources. The effectiveness of a power management scheme depends critically on an accurate modeling of the environment, and on the computation of the control policy. This paper presents two methods for characterizing nonstationary service requests by means of a prediction scheme based on sliding windows. Moreover; it describes how control policies for nonstationary models can be derived.

This paper presents JavaCAD, a new Java-based CAD framework for the design, validation and simulation of systems using third-party components with reciprocal intellectual property (IP) protection. The designer can use remote components with a dedicated and secure Internet protocol, that guarantees IP protection and supports a smooth transition between component evaluation and purchase.

We propose a new RTL power macromodel that is suitable for re-configurable, synthesizable soft-macros. The model is parameterized with respect to the input data size (i.e., bit-width), and can be automatically scaled with respect to different technology libraries and/or synthesis options. Scalability is obtained through a single additional characterization run, and does not require the disclosure of any intellectual property. The model is derived from empirical analysis of the sensitivity of power on input statistics, input data size and technology. The experiments prove that, with limited approximation, it is possible to de-couple the effects on power of these three factors. The proposed solution is innovative, since no previous macromodel supports automatic technology scaling, and yields estimation errors within 15%.

In this work we propose an exact technique for efficient computation of signal statistics during high-level synthesis for low-power of general control-dominated designs. Our approach does not require iterative simulation: simulation is performed once for all to collect boundary information that will be repeatedly exploited for computing signal statistics for alternative implementations.

Dynamic power management schemes (also called policies) reduce the power consumption of complex electronic systems by trading off performance for power in a controlled fashion, taking system workload into account. In a power-managed system it is possible to set components into different states, each characterized by performance and power consumption levels. The main function of a power management policy is to decide when to perform component state transitions and which transition should be performed, depending on system history, workload, and performance constraints. In the past, power management policies have been formulated heuristically. The main contribution of this paper is to introduce a finite-state, abstract system model for power-managed systems based on Markov decision processes. Under this model, the problem of finding policies that optimally tradeoff performance for power can be cast as a stochastic optimization problem and solved exactly and efficiently. The applicability and generality of the approach are assessed by formulating the Markov model and optimizing power management policies for several systems.

Dynamic power management schemes (also called policies) can be used to control the power consumption levels of electronic systems, by setting their components in different states, each characterized by a performance level and a power consumption. In this paper, we describe power-managed systems using a finite-state, stochastic model. Furthermore, we show that the fundamental problem of finding an optimal policy which maximizes the average performance level of a system, subject to a constraint on the power consumption, can be formulated as a stochastic optimization problem called policy optimization. Policy optimization can be solved exactly in polynomial time (in the number of states of the model). We implemented a policy optimization tool and tested the quality of the optimal policies on a realistic case study.

We propose a new approach to RT-level power modeling for combinational macros, that does not require simulation-based characterization. A pattern-dependent power model for a macro is analytically constructed using only structural information about its gate-level implementation. The approach has three main advantages over traditional techniques: (i) it provides models whose accuracy does not depend on input statistics, (ii) it offers a wide range of tradeoff between accuracy and complexity, and (iii) it enables the construction of pattern-dependent conservative upper bounds.

4flamiCP0wer ~~asemeflr ~a desisnmethodology airnins at con!rollins pe@or- rnance and power lmek of disital circreiLcand ~stems, with the soul of eztendins Ihe metonomowoperation time of batte~-powered~stems, providing srac~lpefornmnce degradation when supply ener~is limited, and adaptins power dtiipation to sat~em,ironmental constraints.We survg ~stem-level dynarnicpower rnanasement techniques.We$nt analyze idlene~de:ectimr and shutdown mechanti for idle hardware resources and we review industtilsrandarh for operatins~~em-baedpower mnasement.We describe w~tem-l~elstOchastic madekfor thepowerlpefonnance behaviorof~stems.Uk an-al}ze different rrrodelins assumptforrsarrdwe ducu theirvalidi~andseneraliy.tit, we descn,be methohfor detenninins optirnumpmver manasementstratesies andafso describe Vuriou validation metho~that can be empbyed to assess the effecttieness of power-~flaseable architectures andtheuociatedpawer-manasementschews. hhoductionDe5gnmetiodo10~wforene~y-efitient~skm-leveldmign are r~iving aninm~ingly large uttmtion.The motivations for such intertit =e rood in the wfdqrmd use of portableelectronic appfirmm (e.g., cellular phones, laptop mmputers, etc.) and in the concerns about the environment impact of elwtronic systems [21] (whether mobile or not).System-1eveldesign must stike the bdanm between providing high service leveh to the users wbile crstifing power ditipation.frrother words, we n~d to incrmsc the energetic efficiencyof electronic systems, as it has been done, by other mms, with other types of engines.Electronic systems are heteroseneoasin nature, by mmbining dighrdwith rmdog circuitry,using semiconductor(e.g., RAhl, WSH memorfcs)and eIectro-mcchrnrid (e.g., disks) stomge resourw, as well as electr~opticaf (e.g., displays) human interfaces.Power nranfigementmust address al) types of resour% io a system The power brddown for a well-known laptop computer [34] shows shah on avemge, 36% of the toti power is consumed by the di~lay, 18% by the hard-disk dtie @D), 1S% by the wireless local area network ~interfa~7% by nms-cdtfd components @eybomd,mouse etc.), and only 21% by digiti ~1 circuitry, mainly memory and central processing unit (@~.Reducing the power in the digitaf mmponerrtsof this laptop by IOXwould reduce the overcRpower conmmption by l= than 20%.hweringsystem-Iecel pow,erwnmmption, wM1epreservingadequatesemiw and pecforrnanceIevek, is a dif6cu1ttask hd~, reducing system pecfocrnance(e.g., by using lower clock rates) is not a desirable option when considering the incs~ingly more elabomta software apphcatfon programs for camputers and fmturea of portable elecmonicdevices.On the other hand, present systems have seved componentswhich are not uhfized at dl times.\Vben such componentsare idle, they cmrbe put in slmp states with reduced (or null) power consumption, with a firrdtd (or null) impact on perfomrmce.~namicpow.rrnana~ement is a design methodologyaiming at conuol~ng perfomrance and power leirels of digitrd circuits and systerrrs,by exploiting the id!en~ of their components.A system is provided with a power rnanaser that monitors the ovetil system and component stare and controfs state trantitinns.The mntrol pro.cedure is dlcd power magement policy.Power rnsnagera a be implemented in P-ion to make digitrd or hard copi~of aU or part of this work for peramraf or &sroom use fs granted without fee pmvidd that copies m not made or disti~ utd for profit or co~er@ advantage and that copies bear this notice and the M station on the &t page To copy oth-, to repubUsh, to ~t on sesvm or to redfstriiute to fists, r-= prior s@c moss =d/or a fee.ICCAD98.San]osc.~USA t CSL -SWord Universi~ hardwme or in softwar% depending on system architecture and constraints.JVfren considering genemf-pupse computer systems, the most na~implementation of the power nranageris softwme-based.h particular, the operatins ~~esn (OS) is the software layer where the manager a be implementedbmt Operatingsystem disected power management (OSPhO is actively supported by industry-tiven standmdi~tion efforts such as Mcrosoft's OnNowinitiative [39] and the Advmrced Configuration and PowerInte&ace (A~D standard proposed by ktel, hficrosoft and Toshiba [3~.JVebeheve that dynamic power mrmagementis a viable approach to reduce power cnnsumprionof Inrge-sde systems under perforrrranmmnstim, becmrsesignificant power waste is ~ociated with idle r=ourm and because of its geneti appfimbiUty.Note that support for dynarrrfcpower management must be provided by the oved system ocganimtion,and system architec~often envisionsystem partitions that enable power nraoagemenLhloreover,system componentsshould bepower manaseable,i.e., the rmmagersfrouldbeable to control their state nf operation.hfarrageablecomponen~ m be buildbyexploitingseved specifictechniques,such as supplyvoltage,frquency and activity control [1].NcerflN to say, dynamic pmverrnrmagernentshouldbe mmplemenrcdby specific chip-level design technfqua for power reduction at the arcbitectrrd level [9], at the ~, Ingic nod circuit Ievek [20, ~and by custotid devim and implementation Sechnologim[2S]. Howe\rer,in this survey we focus exclusively on dynamic power rnanagemenL\Ve mrtsider 6rst system-level design issues, such as idleness detection and shutdmvn mechanisms for idle resourw.JVe review the OnNow and A~I standmds, as well as previous work in the as= of power msrragemenL NLKLwe review system-level modehng techniques, and introduce stochastic models for the pov~er/pefimmanwbehavior of systems.\Ve nnd~different modefingmsumptiorss and we discuss their vtidfty.\Ve then consider a working model, for which optiti poficiesabecnmputed,aodw)e discuss howpcdfcicsa beimplementedin electrode systems.ht but not IeasGwe describe seved methods for vaffdatingthe pohcies, based on simulation at different abstmction levefs.JVemncludeby stressing the need for ~teak to support rtrodelidentification, pohcy optitition and tidation for dynarzricaflypower-mmagti systems.

Article Free Access Share on Node sampling: a robust RTL power modeling approach Authors: Alessandro Bogliolo DEIS - Università di Bologna - Italy DEIS - Università di Bologna - ItalyView Profile , Luca Benini DEIS - Università di Bologna - Italy DEIS - Università di Bologna - ItalyView Profile Authors Info & Claims ICCAD '98: Proceedings of the 1998 IEEE/ACM international conference on Computer-aided designNovember 1998 Pages 461–467https://doi.org/10.1145/288548.289071Online:01 November 1998Publication History 9citation131DownloadsMetricsTotal Citations9Total Downloads131Last 12 Months3Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Most work to date on power reduction has focused at the component level, not at the system level. In this paper, we propose a framework for describing the power behavior of system-level designs. The model consists of a set of resources, an environmental workload specification, and a power management policy, which serves as the heart of the system model. We map this model to a simulation-based framework to obtain an estimate of the system's power dissipation. Accompanying this, we propose an algorithm to optimize power management policies. The optimization algorithm can be used in a tight loop with the estimation engine to derive new power-management policy algorithms for a given system-level description. We tested our approach by applying it to a real-life low-power portable design, achieving a power estimation accuracy of ∼10%, and a 23% reduction in power after policy optimization.

In this paper, we propose a robust register-transfer level (RTL) power modeling methodology for functional units. Our models are consistently accurate over a wide range of input statistics, they are automatically constructed and can provide pattern-by-pattern power estimates. An additional desirable feature of our modeling methodology is the capability of accounting for the impact of technology variations, library changes and synthesis tools. Our methodology is based on the concept of node sampling, as opposed to more traditional approaches based on input sampling.

In this paper, we present a new gate-level approach to power and current simulation. We propose a symbolic model of complementary metal-oxide-semiconductor (CMOS) gates to capture the dependence of power consumption and current flows on input patterns and fan-in/fan-out conditions. Library elements are characterized and their models are used during event-driven logic simulation to provide power information and construct time-domain current waveforms. We provide both global and local pattern-dependent estimates of power consumption and current peaks (with accuracy of 6 and 10% from SPICE, respectively), while keeping performance comparable with traditional gate-level simulation with unit delay. We use VERILOG-XL as simulation engine to grant compatibility with design tools based on Verilog HDL. A Web-based user interface allows our simulator (PPP) to be accessed through the Internet using a standard web browser.

PPP is a Web-based simulation and synthesis environment for low-power design.In this paper we describe the gate-level simulation engine of PPP, that achieves accuracy always within 6% from SPICE, while keeping performance c ompetitive with traditional gate-level simulation.This is done by using advanced symbolic models of the basic library cells, that exploit the physical understanding of the main powerconsuming phenomena.VERILOG-XL is used as simulation platform to maintain compatibility with design environments.The Web-based interface allows the user to remotely access and execute the simulator using his/her own Webbrowser (without the need of any software installation).

We describe a paradigm for integrating EDA tools running on distributed platforms under a common user interface. We focus on interactive remote execution more than on simple information retrieval. Minimum support is required on the user side to access the features offered by a large and diverse set of tools: the user's WWW browser is the interface for all interactions. Integrating new tools in the environment is a straightforward process that does not require any effort from the end users. The learning curve is extremely short because the well-known user interface provided by the WWW browser is exploited. PPP is a prototype we implemented to show the feasibility of WWW-based tool integration. We describe the features of PPP, its architecture and its implementation.

We present a new gate-level approach to current simulation. We use a symbolic model of current pulses that takes accurately into account the dependence on the switching conditions. We then construct current waveforms during event-driven logic simulation by means of pulse composition. We obtain satisfying accuracy on time-domain current waveforms and on peak current estimates, while maintaining performance comparable with traditional gate-level simulation.

The presence of large current peaks on the power and ground lines is a serious concern for designers of synchronous digital circuits. Current peaks are caused by the simultaneous switching of highly loaded clock lines and by the signal propagation through the sequential logic elements. In this work we propose a methodology for reducing the amplitude of the current peaks. This result is obtained by clock skew optimization. We propose an algorithm that determines the clock arrival time at each flip-flop in order to minimize the current peaks while respecting timing constraint. Our results on benchmark circuits show that current peaks can be reduced by more than a factor of two without penalty on cycle time and average power dissipation. Our methodology is therefore well-suited for low-power systems with reduced supply voltage, where low noise margins are a primary concern.

In this paper we present a new approach to the design of circuits with special properties with regards to internal faults, such as self-checking and fault-tolerant circuits. The approach is based on introducing a minimal amount of redundancy during a multilevel logic optimization process. In this process, we take advantage of the degrees of freedom associated with internal don't care conditions, in order to minimize the amount of redundancy needed to achieve the desired fault-handling capabilities. Experimental results on several benchmark circuits are presented. They compare very favourably with traditional implementations based on topological augmentation rules.

This paper presents new algorithms for evaluating the reliability of fault-tolerant combinational logic circuits. In order to model the effects of multiple faults on circuit functionality, we use fault indicators as control variables. We use BDD-based symbolic simulation to avoid the explicit enumeration of faults. We present experimental results on fault-tolerant implementations of several mcnc benchmark circuits. They show that undetectable multiple faults have a large impact on the reliability of fault-tolerant circuits.