In this paper we describe a common problem when it comes to mutual authentication of devices in smart environments. Basically, there exist two approaches. In the brokered approach, two parties authenticate with the help of a common trusted party. However, this often introduces a single point of failure. The alternative approach lets the devices authenticate with each other directly, usually by exchanging a shared secret out of band. But this is only possible if both devices have the necessary user interface peripherals to establish an out-of-band channel. We will describe an abstract basic protocol to bridge the possible peripherals' gaps by authenticating indirectly with the help of nowadays basically omnipresent multimedia devices such as smart phones. After extending the proposed protocol for more complex use cases, we refine it to a practical authenticated key establishment protocol for indirect authentication. Finally we describe our freely available prototype implementation consisting of an internet-of-things-enabled light bulb and light switch and an Android app that comprise our proof of concept.

What visions of technologies such as the Internet of Things (IoT), Pervasive Computing (PC) or Ambient Intelligence (AI) have in common is that they employ a very high amount of critically resource-constrained devices. This of course raises a whole set of new security challenges. Instead of proposing another middleware for IoT, PC or AI, and presenting a security approach for it we focus on existing, widely-adopted security mechanisms and concepts and give a comprehensive overview. Furthermore, we examine the Web Service security suite as an example for a comprehensive security framework on application level. We use an intentionally kept simple scenario including light bulbs and switches to demonstrate necessary security mechanisms and properties and to judge applicability of the presented existing security techniques and frameworks.

This paper addresses the question of how to handle irreducible regions during optimization, which has become even more relevant for contemporary processors since recent VLIW-like architectures highly rely on instruction scheduling. The contributions of this paper are twofold. First, a method of optimized node splitting to transform irreducible regions of control flow into reducible regions is formally defined and its correctness is shown. This method is superior to approaches previously published since it reduces the number of replicated nodes by comparison. Second, three methods that handle regions of irreducible control flow are evaluated with respect to their impact on compiler optimizations. First, traditional node splitting is evaluated. Second, optimized node splitting is implemented. Third, DJ-Graphs are utilized to recognize nesting of irreducible (and reducible) loops and apply common loop optimizations extended for irreducible loops. Experiments compare the performance of these approaches with unrecognized irreducible loops that cannot be subject to loop optimizations, which is typical for contemporary compilers. Measurements show improvements of 1 to 40% for these methods of handling irreducible loops over the unoptimized case. Optimized node splitting may be chosen to retrofit existing compilers since it has the advantage that it only requires few changes to an optimizing compiler while limiting the code growth of compiled programs compared to traditional node splitting. Recognizing loops via DJ-Graphs should be chosen for new compiler developments since it requires more changes to the optimizer but does not significantly change the code size of compiled programs while yielding comparable improvements. Handling irreducible loops should even yield more benefits for exploiting instruction-level parallelism of modern architectures in the context of global instruction scheduling and optimization techniques that may introduce irreducible loops, such as enhanced modulo scheduling.

This paper addresses the question of how to handle irreducible regions during optimization, which has become even more relevant for contemporary processors since recent VLIW-like architectures highly rely on instruction scheduling. The contributions of this paper are twofold. First, a method of optimized node splitting to transform irreducible regions of control flow into reducible regions is derived. This method is superior to approaches previously published since it reduces the number of replicated nodes by comparison. Second, three methods that handle regions of irreducible control flow are evaluated with respect to their impact on compiler optimizations: traditional and optimized node splitting as well as loop analysis through DJ graphs. Measurements show improvements of 1-40% for these methods of handling irreducible loop over the unoptimized case.