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Anthony E. Parker

dblp:40/2158 · DBLP profile ↗
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6ranked-venue papers
3as first author
0since 2021 · last 1995
0000-0001-5514-4077ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 6 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 50% Electronic design automation · 50%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
analog and mixed-signal circuits
0.011990
An improved FET model for computer simulators · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990
Electronic design automation
circuit simulation
0.011990
An improved FET model for computer simulators · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990
Electronic design automation › circuit modeling
device model
0.011990
An improved FET model for computer simulators · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990
Integrated circuit design › semiconductor device modeling
FET modeling
0.011990
An improved FET model for computer simulators · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990

Methods — techniques the papers use, named apart from their topics

empirical polynomial expression · 0.0
YearPublicationVenuePosition
1995 Novel Circuit Synthesis Technique Using Short Channel GaAs Fets Giving Reduced Intermodulation Distortion
abstract
We present graphically a novel FET synthesis technique based on the derivative structure observed in real GaAs MESFETs. The synthesis allows the generation of continuously differentiable linear or nonlinear transfer characteristics.
D. R. Webster, David G. Haigh, Anthony E. Parker
ISCAS3
1994 Distortion Compensation of Multi-Mesfet Circuits
abstract
We present an analysis of a 4-FET Transconductor at medium frequencies, using a more realistic GaAs MESFET model, to calculate optimum device widths to minimise 2nd order distortion. Provisional analytical results are compared with SPICE simulations using the Parker Skellern model. A multi-FET Frequency Doubler is similarly analysed to calculate optimum device widths for high fundamental rejection and optimum load for 3rd order distortion nulling. The high frequency degradation of the 4-FET Transconductor is discussed. Simulated performance of two high frequency distortion compensated Linearised Isolator designs, together with a variation of the Frequency Doubler, show good performance at high frequencies.>
D. R. Webster, David G. Haigh, Anthony E. Parker
ISCAS3
1994 Device Circuit Interaction in the Common Source Amplifier
abstract
The non-linearity demonstrated by a circuit is a function of the device nonlinearity, its parasitic components and the circuit components in which it is embedded. We demonstrate that the common source stage, which is used extensively for Device Characterisation, presents a very complex form of Device-Circuit Interaction, which makes reliable extraction of its intrinsic non-linear parameters extremely difficult. We show how pulse measurements can provide a straight forward access to parameters needed for Volterra Analysis and show the true nature of output conductance.>
D. R. Webster, Anthony E. Parker, David G. Haigh, Paul M. Radmore
ISCAS2
1993 Compensation of 2nd Harmonic Distortion in a 4-FET Linearised Transconductor Circuit
Anthony E. Parker, David G. Haigh
ISCAS1
1993 New Method for Comprehensive Characterisation of MES/MOD/MOS FET's
Anthony E. Parker, Jonathan B. Scott
ISCAS1
1990 An improved FET model for computer simulators
abstract
Described is an alternative simple description of FET drain current that provides the flexibility of an extra parameter which can be chosen to approximate the Shockley expression or general power law. An empirical polynomial expression which uses only integer powers is used to provide computational efficiency. The expression gives the designer a more accurate FET model which is consistent for both large- and small-signal simulations.>
Anthony E. Parker, David J. Skellern
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1