In this paper, a novel and highly efficient inexact Full Adder cell by exploiting two logic styles including conventional CMOS (C-COMS) and pass transistor logic (PTL) are presented. The so-called carbon nanotube field-effect transistor (CNFET) technology is used to implement circuits at the transistor level. To justify the efficiency of our design, extensive simulations are performed at the transistor level as well as application level. Transistor-level simulations which are carried out by the HSPICE 2008 tool, demonstrate at least 12% higher performance in terms of power-delay-area product (PDAP) of the proposed circuit compared to the latest designs. At the application level, by using the MATLAB tool, inexact Full Adders are employed in the structure of the ripple carry adder (RCA) that is applied in motion and edge detection algorithms. Computer simulation results confirm the appropriate quality of the output images in terms of the peak signal-to-noise ratio (PSNR) and structural similarity (SSIM) criteria. At last, to make a compromise between hardware and application level parameters, the power-delay-area-1/PSNR product (PDAPP) and power-delay-area-1/SSIM product (PDASP) are considered as figures of merit. The proposed circuit shows remarkable improvement from the PDAPP and PDASP points of view compared to its counterparts.

Below 45nm technology, process variation causes the occurrence of unpredictable characteristics in fabricated transistors. In this paper, a platform has been developed to examine Die-to-Die process and environment variations impacts on power and delay of network-on-chip routers. As a benchmark an asynchronous router will be considered. To reduce power, Power Delay Product (PDP) and variability of this router, three approaches, namely Suitable Sizing, Stacking and Dual-Vth are proposed. By using Suitable Sizing and applying Stacking approaches on input ports of a particular router configuration, power and PDP are reduced by 41.37% and 39.31%, respectively, for 3.63% delay increase only. Simultaneous use of Dual-Vth and Suitable Sizing approaches in one of the router configurations causes the reduction of power and PDP by 27.74% and 26.54%, respectively, for a delay overhead of 1.74%. Our proposed approaches reduce the router variability to some parameters variation such as Vdd, Vth, and PMOS and NMOS transistors length.

This paper proposes a high-level test generation method which considers the control part as well as data path of a register transfer level circuit as a set of polynomial functions to generate behavioral test patterns from faulty behavior instead of comparing the faulty and fault-free circuits based on a hybrid Boolean-word canonical representation called Horner expansion diagram. Since this set of polynomial functions express primary outputs and next states with respect to primary inputs and present states, it is not necessary to perform justification/propagation phase which leads to a minimum number of backtracks. It improves fault coverage and reduces test generation time over logic-level techniques. We assess then the effectiveness of high-level test generation with a simple gate-level automatic test pattern generation algorithm. Experimental results show robustness and reliability of our method compared to other contemporary approaches in terms of fault coverage and CPU time.