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Huan-Yu Tu

dblp:40/2815 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 2001
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Interconnection networks and networks-on-chip · 70% Hardware reliability and fault tolerance · 30%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware reliability and fault tolerance › network fault tolerance
fault-tolerant network design
0.012001
Families of Optimal Fault-Tolerant Multiple-Bus Networks · IEEE Trans. Parallel Distributed Syst. 2001
Interconnection networks and networks-on-chip › routing algorithms
fault-tolerant routing
0.012001
Families of Optimal Fault-Tolerant Multiple-Bus Networks · IEEE Trans. Parallel Distributed Syst. 2001
Interconnection networks and networks-on-chip › bus-based interconnection
multiple bus network
0.012001
Families of Optimal Fault-Tolerant Multiple-Bus Networks · IEEE Trans. Parallel Distributed Syst. 2001
Interconnection networks and networks-on-chip › interconnect architecture
scalable interconnect
0.012001
Families of Optimal Fault-Tolerant Multiple-Bus Networks · IEEE Trans. Parallel Distributed Syst. 2001

Methods — techniques the papers use, named apart from their topics

fault-tolerant routing algorithm · 0.0
YearPublicationVenuePosition
2001 Families of Optimal Fault-Tolerant Multiple-Bus Networks
abstract
Optimally fault-tolerant partial-connection multiple-bus networks and their fault-tolerant routing algorithms are presented in this paper. The proposed networks are scalable and provide flexibility in the choice of network parameters determining construction cost, system performance, and fault tolerance, given a fixed number of processors. In this design, when performance begins to fall due to contention, the simple addition of a bus can improve performance without adding costly processors or changing the whole topology, as required for other multiple-bus designs. Also, in situations requiring high reliability, for a fixed number of processors, excellent fault tolerance can be obtained.
Huan-Yu Tu, Lois Wright Hawkes
IEEE Trans. Parallel Distributed Syst.1
1999 Network Simulations of a General Class of Partial-Connection Multiple-Bus Systems
abstract
A general class of optimal fault-tolerant partial-connection multiple-bus networks and their self-routing algorithms has been developed (Huan-yu Tu, 1999). By conducting a large number of network simulations, using self-similar traffic we compare the performance of these networks with those of traditional single-bus networks and complete-connection multiple-bus networks. Our simulation results show that given a fixed number of processors, these partial-connection networks have improved performance over single-bus systems, perform comparably to the more costly complete-connection multiple-bus systems, and have flexibility in setting the performance level and fault-tolerance level. Moreover, we demonstrate that, in certain of these networks, if the system load increases resulting in decreased performance, this can be handled by adding buses to the system rather than completely changing the topology. Thus, for very little additional cost and no change of topology or routing algorithm, increased loads are handled.
Huan-Yu Tu, Lois Wright Hawkes
MASCOTS1