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Manjusha Shankaradas

dblp:40/2913 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2003
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
analog and mixed-signal circuits		 0.012003
Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL · DAC 2003
Integrated circuit design
low-power circuit design		 0.012003
Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL · DAC 2003
Integrated circuit design › analog and mixed-signal circuits › mixed-signal circuit design
phase-locked loop		 0.012003
Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL · DAC 2003

Methods — techniques the papers use, named apart from their topics

sampled feed-forward filter · 0.0programmable current mirror · 0.0
YearPublicationVenuePosition
2003 Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL
abstract
A self-biased PLL uses a sampled feed-forward filter network and a multi-stage inverse-linear programmable current mirror for constant loop dynamics that scale with reference frequency and are independent of multiplication factor, output frequency, and PVT. The PLL achieves a multiplication range of 1 to 4096 with less than 1.7% output jitter. Fabricated in 0.13μm CMOS, the area is 0.182mm2 and the supply is 1.5V.
John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey, Manjusha Shankaradas
 DAC5