Demo Data from VLDB 2026 / reviewers in the wild / expert
Jan Butas
dblp:40/3223
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2001
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 100% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
asynchronous circuit design |
0.0 | 1 | 2001 | A New Control Circuit for Asynchronous Micropipelines · IEEE Trans. Computers 2001 |
Integrated circuit design › asynchronous circuit design
micropipeline |
0.0 | 1 | 2001 | A New Control Circuit for Asynchronous Micropipelines · IEEE Trans. Computers 2001 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2001 | A New Control Circuit for Asynchronous MicropipelinesabstractIn this paper, we present a new configuration of an asynchronous micropipeline, called locally distributed asynchronous (LDA) micropipeline, using a new control circuit. The control circuit generates local control signals according to the 4-phase signaling protocol. The control circuit is used to control the dynamic logic in the datapath. Comparisons based on simulations with other earlier published asynchronous micropipelines are also presented. Oliver Chiu-sing Choy, Jan Butas, Juraj Povazanec, Cheong-Fat Chan |
IEEE Trans. Computers | 2 |
| 2000 | An ALU design using a novel asynchronous pipeline architectureabstractThis paper presents a design of a 16-bit pipeline ALU. The ALU is implemented by using a novel asynchronous pipeline architecture. The architecture has simple handshake cells and these cells are embedded in the pipeline stage as normal logic cells. As a result, the speed of the ALU can be very fast. Tin-Yau Tang, Oliver Chiu-sing Choy, Jan Butas, Cheong-Fat Chan |
ISCAS | 3 |