The old school of analog designers, exemplified by pioneer Bob Pease, is becoming an extinct species. But the demand for analog/mixed-signal IP blocks has never been greater, especially at 65 nm and below. Can this demand be met by using externally designed 3rdparty analog/mixed-signal IP? Or is the implementation of revolutionary changes to traditional work flows and analog design processes a suitable option? Which solutions that help in increasing design efficiency are currently on the table? In the future, which side of the table would analog designers of Bob Pease's generation sit: the IP provider or the chip company? Or are their skills redundant for the 65 nm analog design challenges?

A semiempirical model for carrier mobility in silicon inversion layers is presented. The model, strongly oriented to CAD (computer-aided design) applications, is suitable for two-dimensional numerical simulations of nonplanar devices. A local mobility function, set up in terms of a simple Mattiessen's rule, provides a careful description of MOSFET operation in a wide range of normal (or gate) electric fields, channel impurity concentrations of between 5*10/sup 14/ cm/sup -3/ and 10/sup 17/ cm/sup -3/ for the acceptor density of states and 6*10/sup 14/ cm/sup -3/ and 3*10/sup 17/ cm/sup -3/ for the donor density of states; and temperatures between 200 K and 460 K. Best-fit model parameters are extracted by comparing the calculated drain conductance with a very large set of experimental data points.>

The Newton iteration method used in conventional numerical device simulations is extended to include bias conditions as variable parameters in the system of semiconductor equations. This extension leads to a very simple algorithm to evaluate low-frequency, small-signal parameters based on dc solutions. It also provides an elegant way to project an initial guess for subsequent bias conditions. Rigorous mathematical derivation and applications to the evaluation of junction capacitance and breakdown voltage are given. The initial guess projection is also illustrated through examples.

It is well known that Meyer's model for the MOST implemented in SPICE does not guarantee charge conservation, while Ward's model seems somewhat complex to be used as a standard for the transient analysis of all the MOS circuits. In this work, a new simple MOST model for the transient analysis of MOS integrated circuits is presented. The model was developed by performing the numerical integration of the gate current as a first step without introducing the concept of a mean constant capacitance. The new model has been implemented in the program SGS-SPICE. All benchmark tests indicate that it conserves the charge at all the terminals of the MOS transistor.