Camouflaged Object Detection (COD) aims to accurately detect objects that blend in with their backgrounds. While deep learning-based methods have significantly improved detection accuracy, the persistent similarity in chromatic and textural characteristics between camouflaged objects and their environments continues to pose substantial challenges, particularly in complex scenarios. Existing COD methods still encounter two primary challenges: (1) the difficulty in effectively fusing detailed features with semantic representations, leading to suboptimal balance between local and global features in the fused features; (2) progressive information dilution in conventional top-down decoder architectures, resulting in imprecise boundary localization. To address these dual challenges of multi-scale feature enhancement and semantic information dilution, we propose a D ual-Branch C ross-Layer I nformation F low Network (DCIFNet) for COD in complex scenes. Specifically, our framework integrates a hybrid CNN-ViT architecture for parallel extraction of localized patterns and global contextual features. Subsequently, a Global Local Fusion (GLF) module is employed to iteratively and adaptively fuse the global and local features at each stage using gating weights. Additionally, a novel Dense Connection Decoder (DCD) module is designed to mitigate the information dilution problem associated with traditional top-down decoders. Extensive experiments show that DCIFNet outperforms other mainstream COD models in most performance metrics on four widely used benchmark datasets. On the COD10K dataset, compared with the latest SOTA work of PRNet, DCIFNet improves the metrics of \({S_{\alpha}}\) , \({E_{\phi}}\) , and \(F_{\beta}^{w}\) by 0.11%, 0.11%, and 1.38%, respectively, demonstrating a significant performance enhancement. The code is available https://github.com/WateverOk/DCIFNet .

Synthetic aperture radar (SAR) target detection has extensively utilized convolutional neural networks (CNNs). Nonetheless, CNN-based methods often achieve favorable detection accuracy at the cost of high model complexity, hindering deployment of the algorithm in real-time application scenarios, such as maritime rescue and military decision making. To deal with this problem, we are the first to propose an ultra-lightweight object detector named Ulit-BiDet for SAR images, which incorporates binary neural network with very low storage and computation costs. First, we creatively design a performance and cost-scalable binary backbone that adapts to the diverse resources and computational capacities on practical devices. Then, the backbone structure is optimized with a new Non-Local Module to enhance semantic contextual information, thereby alleviating false detections caused by the interference from land clutter and sea clutter. Third, considering the SAR imaging mechanism, the interference near the ship boundary with similar scattering power probably affects the localization accuracy due to the interfered object-related contour information. To tackle the localization issue, we uniquely propose to utilize valuable and extra object-related contour semantics to guide representation learning of ship targets. The scheme compels the model to generate features that highlight object contour, thereby promoting accurate boundary localization in ship target detection. We validated the robustness of the proposed network in three mostly-cited publicly available datasets. Experimental results demonstrate that our model achieves 97.2%, 95.2%, and 77.3% detection accuracy with only 1.27M parameters and 0.22G OPs on SSDD, SAR-Ship, and AIR–SARShip2.0 ship detection datasets, respectively.

Quantization has become a popular technique to compress deep neural networks (DNNs) and reduce computational costs, but most prior work focuses on training DNNs at each individual fixed bit-width and accuracy trade-off point. How to produce a model with flexible precision is largely unexplored. This work proposes a multi-bit quantization framework (MultiQuant) to make the learned DNNs robust for different precision configuration during inference by adopting Lowest-Random-Highest bit-width co-training method. Meanwhile, we propose an online adaptive label generation strategy to alleviate the problem of vicious competition under different precision caused by one-hot labels in the supernet training. The trained supernet model can be flexibly set to different bit widths to support dynamic speed and accuracy trade-off. Furthermore, we adopt the Monte Carlo sampling-based genetic algorithm search strategy with quantization-aware accuracy predictor as evaluation criterion to incorporate the mixed precision technology in our framework. Experiment results on ImageNet datasets demonstrate MultiQuant method can attain the quantization results under different bit-widths comparable with quantization-aware training without retraining.

Field-programmable gate array (FPGA)-based accelerators for convolutional neural network (CNN) inference have received significant attention in recent years. The reported designs tend to adopt a similar underlying approach based on multiplier-accumulator (MAC) arrays, which yields strong demand for the available on-chip DSP blocks, while leaving FPGA logic and memory resources underutilized. The practical outcome is that the computational roof of the accelerator is bound by the number of DSP blocks offered by the target FPGA. In addition, integrating the CNN accelerator with other functional units that may also need DSP blocks would degrade the inference performance. Leveraging the robustness of inference accuracy to limited arithmetic precision, we propose a transformation to the convolution computation, which leads to transformation of the accelerator design space and relaxes the pressure on the required DSP resources. Through analytical and empirical evaluations, we demonstrate that our approach enables us to strike a favorable balance between utilization of the FPGA on-chip memory, logic, and DSP resources, due to which, our accelerator considerably outperforms state of the art. We report the effectiveness of our approach on a variety of FPGA devices, including Cyclone-V, Stratix-V, and Arria-10, which are used in large number of applications, ranging from embedded settings to high performance computing. Our proposed technique yields 1.5x throughput improvement and 4x DSP resource reduction compared to the best frequency domain convolution-based accelerator, and 2.5x boost in raw arithmetic performance and 8.4x saving in DSPs compared to a state-of-the-art sparse convolution-based accelerator.

Hardware accelerators for convolutional neural network (CNN) inference have been extensively studied in recent years. The reported designs tend to utilize a similar underlying architecture based on multiplier-accumulator (MAC) arrays, which has the practical consequence of limiting the FPGA-based accelerator performance by the number of available on-chip DSP blocks, while leaving other resource under-utilized. To address this problem, we consider a transformation to the convolution computation, which leads to transformation of the accelerator design space and relaxes the pressure on the required DSP resources. We demonstrate that our approach enables us to strike a judicious balance between utilization of the on-chip memory, logic, and DSP resources, due to which, our accelerator considerably outperforms state of the art. We report the effectiveness of our approach on a Stratix-V GXA7 FPGA, which shows 55% throughput improvement, while using 6.25% less DSP blocks, compared to the best reported CNN accelerator on the same device.

This paper implements an OpenCL-based FPGA accelerator for YOLOv2 on Arria-10 GX1150 FPGA board. The hardware architecture adopts a scalable pipeline design to support multi-resolution input image, and improves resource utilization by full 8-bit fixed-point computation and CONV+BN+Leaky-ReLU layer fusion technology. The proposed design achieves a peak throughput of 566 GOPs under 190 MHz working frequency. The accelerator could run YOLOv2 inference with 288×288 input resolution and tiny YOLOv2 with 416×416 input resolution at the speed of 35 and 71 FPS, respectively.

Convolutional neural networks (CNNs) have been employed in many applications, such as image classification, video analysis and speech recognition. Being compute-intensive, CNNs are widely accelerated by GPUs with high power dissipations. Recently, studies were carried out exploiting FPGA as CNN accelerator because of its reconfigurability and advantage on energy efficiency over GPU, especially when OpenCL-based high-level synthesis tools are now available providing fast verification and implementation flows. In this paper, we demonstrate PipeCNN - an efficient FPGA accelerator that can be implemented on a variety of FPGA platforms with reconfigurable performance and cost. The PipeCNN project is openly accessible, and thus can be used either by researchers as a generic framework to explore new hardware architectures or by teachers as a off-the-self design example for any academic courses related to FPGAs.

A mixed-grained reconfigurable computing platform targeting multiple-standard video decoding is proposed in this paper. The platform integrates eight coarse-grained Reconfigurable Processing Units (RPUs), each of which consists of 16×16 multi-functional Processing Elements (PEs) and are implemented in TSMC 65 nm technology and two Altera Stratix IV EP4SE820 FPGAs. By exploiting dynamic reconfiguration of the RPUs and static reconfiguration of the FPGAs, the proposed platform achieves scalable performances and cost trade-offs to support a variety of video coding standards, including H.264, MPEG-2, AVS and HEVC. Two types of platform configuration are tested in this work. One configuration utilizes two RPUs and targets multiple-standard high-definition (HD) video decoding, while the other utilizes only one RPU, which works under a lower frequency and targets at standard resolution (SD) decoding. The HD configuration can decode 1920×1080 H.264 video streams at 30 frames per second (fps) under 200 MHz and 1920×1080 HEVC video streams at 30 fps under 236 MHz. It achieves a 25% performance gain over an industrial coarse-grained reconfigurable processor for H.264 decoding, and a 3.85× performance boosts over the Intel i5 general-purpose CPU for HEVC decoding.

A coarse-grained reconfigurable processing unit (RPU) consisting of 16 ×16 multi-functional processing elements (PEs) interconnected by an area-efficient line-switched mesh connect (LSMC) routing is implemented on a 5.4 mm ×3.1 mm die in TSMC 65 nm LP1P8M CMOS technology. A hierarchical configuration context (HCC) organization scheme is proposed to reduce the implementation overhead and the energy dissipation spent on fast reconfiguration. The proposed RPU is integrated into two system-on-a-chips (SoCs), targeting multiple-standard video decoding. The high-performance chip, comprising two RPU processors (named REMUS_HPP), can decode 1920 ×1080 H.264 video streams at 30 frames per second (fps) under 200 MHz. REMUS_HPP achieves a 25% performance gain over the XPP-III reconfigurable processor with only 280 mW power consumption, resulting in a 14.3 × improvement on energy efficiency. The other chip (named REMUS_LPP), targeting low power applications, integrates only one RPU processor. REMUS_LPP can decode 720 ×480 H.264 video streams at 35fps with 24.5 mW under 75 MHz, achieving a 76% reduction in power dissipation and a 3.96 × improvement on energy efficiency compared with the ADRES reconfigurable processor.

The existing cognitive radio networks (CRNs) lack the ability to deal with the electronic attack of malicious users, which can destroy the normal communication of the cognitive users. To solve the problem, we propose a novel secure CRN by combining MIMO technique and low density parity check (LDPC) codes at the base-station (BS) and mobile stations (MSs), the electronic interference of the malicious users can be effectively weakened. The capacity and the outage probability of the proposed MIMO CRN are analyzed. The simulation results in quasi-static Rayleigh flat-fading channel show that the proposed secure MIMO CRN can effectively cancel electronic interference from the malicious users.

The existing cognitive network (CN) nodes do not support Differentiate-Serve (Diffserv) Quality of Service (QoS), and the existing Diffserv QoS scheme has not considered the link capacities between UDP subscribers and TCP subscribers of CN nodes. To solve these problems, a Diffserv CN node and Controlled-UDP (C-UDP) based fluid model are proposed for hybrid traffics' CN. The proposed C-UDP and CN node limit the data rates of UDP subscribers according to their priorities, and allocate the link capacities to different classes of TCP traffics and C-UDP traffics. The dynamic simulation results demonstrate the proposed CN node and C-UDP for the TCP/UDP hybrid traffics for CN to be valid.

This paper presents a new scheme for evaluating complex reciprocal and exponential functions in hardware. The proposed method utilizes a two-dimensional convolution algorithm to interpolate bivariate functions from tabulated function values in the complex domain. To reduce the memory requirements for lookup tables, the interpolation is decomposed into independent row and column computations, such that the same coefficient table can be shared. Three different interpolation kernels from degree-1 (linear) to degree-2 (quadratic Lagrange) and degree-3 (cubic Lagrange) are explored to find the optimal design parameters and the most acceptable trade-offs between performance and hardware resources. Moreover, a generic hardware architecture is designed to provide scalable implementation capabilities for computation precision and interpolation degree. To verify the proposed architecture, eight complex reciprocal and eight complex exponential design instances are implemented. The ASIC- and FPGA-based experimental results show that the proposed scheme can efficiently approximate the complex reciprocal and exponential functions with up to 16-bit precision, as well as achieve a considerable reduction of memory requirements compared with traditional bipartite and multipartite schemes. The proposed method is also applicable to other complex functions.

To assist the system architects with fast exploration and performance evaluation of the reconfigurable software/hardware architectures, this paper presents a system-level simulator, named after SimRPU, for the reconfigurable processing unit (RPU), which is the major computing engine in reconfigurable processor. The proposed simulator consists of a simulation kernel, a software compiler, a system profiler providing performance, area and power information for the desired architectures, and a system debugger supporting inspecting and modification of the internal state of the RPU. Object-oriented hierarchical and parameterized architecture modeling techniques are proposed to satisfy the requirements for a fast and comprehensive evaluation. Cycle-accurate simulation mechanisms are developed to improve the accuracy of the profiled performance data. Compared with the traditional register transfer level (RTL) based simulation scheme, the proposed simulator could achieve an average speedup of 18.5× with only 3.5% reduction on performance estimation accuracy. One reconfigurable processor targeted at high-definition multimedia decoding applications (such as H.264, MPEG2, AVS, etc.) is implemented with Taiwan Semiconductor Manufacturing Company 65-nm process using the proposed exploration and design flow. The measured results show that the implemented architecture has obvious advantages in terms of both performance and power consumption than the reference designs in multimedia decoding applications.

This paper proposed a THPHP (Task-based Hybrid Parallels and Hybrid Pipelines) scheme to implement multistandard video decoding algorithms, i.e. MPEG-2, H.264 and AVS (Audio Video coding Standard), on a heterogeneous coarsegrained reconfigurable multimedia processor called REMUS (REconfigurable MUltimedia System). Multiple level parallelism and multiple level pipeline techniques are proposed in this scheme. Simulation results show that the video decoder can support H.264 HP (High Profile) 1920×1080@30fps (frame per second) streams, AVS JP (Jizhun Profile) 1920×1080@39fps streams, and MPEG-2 MP (Main Profile) 1920×1080@41fps streams when exploiting a 200MHz working frequency.

Emerging techniques and systems for Wireless Sensor Network (WSN) are developed in the last decade for various application fields. In WSN, the sensor nodes are usually distributed over a large area and are powered by batteries with limited energy, maintaining a long service lifetime for the entire network becomes a challenging task. In this paper, a novel battery aware MAC analytical model is proposed for low duty-cycled WSN. The proposed analytical model takes the characteristics of actual battery into account and targets the optimal sleep interval with a reasonable trade-offs between the energy dissipation on sending the preamble and idle listening. The simulation results demonstrate that the proposed approach can improve the energy efficiency as well as guarantee low latency and high reliability.

We present a novel design of a radix-16 combined unit for complex division and square root in fixed-point format. A new digit-recurrence algorithm with two-step operand prescaling is developed for complex square root to avoid postscaling of the result. A combined recurrence algorithm is generalized and a scalable hardware architecture is proposed. Designs with different operand precision are implemented in Altera Stratix-II FPGA and cost and performance are evaluated and compared with reference designs of complex division or square root implemented combined or separately. The results show advantages of the proposed combined design in cost and performance.

We present a design of a radix-8 complex division for fixed-point operands suitable for FPGA implementation. The design, consisting of operands' prescaling and digit recurrence, shares logic resources and optimizes the use of 6-input LUTs of FPGA devices for efficient design. An optimized single table for prescaling factors is developed. The design is implemented in Altera Stratix-II FPGA for several operands precisions and compared in cost, latency and power with a design using non-shared resources and with an IP-based design. The results show advantages of the proposed design in cost, delay, and power.