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Mark A. Heap

dblp:40/4252 · DBLP profile ↗
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4ranked-venue papers
4as first author
0since 2021 · last 1994
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 4 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Theoretical computer science
1 paper
Logic in computer science · 77% Coding theory · 23%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Logic in computer science › algebraic logic › boolean algebra › boolean function representation
ordered binary decision diagram
0.011994
Least Upper Bounds an OBDD Sizes · IEEE Trans. Computers 1994
Coding theory › error-correcting codes › decoding › minimum distance decoding
bounded-distance decoding
0.011994
Least Upper Bounds an OBDD Sizes · IEEE Trans. Computers 1994

Methods — techniques the papers use, named apart from their topics

combinatorial analysis · 0.0
YearPublicationVenuePosition
1994 Least Upper Bounds an OBDD Sizes
abstract
This paper derives exact equations for the maximum number of nonterminal vertexes in reduced and quasi-reduced ordered binary decision diagrams (OBDD's). A reduced OBDD is reduced by both merging and deleting vertices, and a quasi-reduced OBDD is reduced only by merging. These formulas are used to tighten Lee's original bounds, and to correct the bounds recently reported by H.T. Liaw and C.S. Lin (1992).>
Mark A. Heap, M. Ray Mercer
IEEE Trans. Computers1
1993 On the exact ordered binary decision diagram size of totally symmetric functions
Mark A. Heap
J. Electron. Test.1
1992 A Synthesis Algorithm for Two-Level XOR Based Circuits
abstract
A fast algorithm for minimizing the two-level AND/XOR representation of combinational functions, based on a graphical data structure similar to the OBDD, is described. This GMX (Graphical Minimizer for XORs) algorithm works by 'reading-off' and minimizing the solution from an augmented OBDD, called an SFG. The advantage of the SFG structure is that it is often of polynomial size. The algorithm generates solutions significantly better, or no worse, than all previously published solutions on a set of example circuits.>
Mark A. Heap, William A. Rogers, M. Ray Mercer
ICCD1
1991 STarS: a target switching algorithm for sequential test generation
abstract
The authors introduce a new deterministic test pattern generation algorithm for sequential circuits. The Sequential Target Switching (STarS) algorithm begins generating a test sequence for a specific target fault, but as each pattern is generated, it keeps track of the set of faults that may also use this sequence as part of a test. Backtracking is avoided by switching the target fault to a member of this fault set, and partial sequences are re-used as much as possible.>
Mark A. Heap, William A. Rogers, William B. Burns
VTS1