Energy harvesting from multiple sources is a more robust method for powering Internet of Things (IoT) nodes and similar wireless systems compared to harvesting from a single source. This work provides a description of an optimization CAD tool for reconfigurable capacitive DC-DC converters with multiple inputs used for energy-harvesting from multiple sources with varying levels of input power. The tool estimates the theoretical maximum efficiency for each converter configuration, along with the input power condition that achieves this performance. In addition, for given values of the available power from the harvesting sources connected to the DC-DC converter inputs, the proposed CAD tool finds the best converter configuration for that power state of the harvesters.

The design of a robust watermarking technique has been always suffering from the conflict between the watermark robustness and the quality of the watermarked image. In this study, the embedding strength parameters for per‐block image watermarking in the discrete cosine transform (DCT) domain are optimised. A fitness function is proposed to best suit the optimisation problem. The optimum solution is selected based on the quality and the robustness achieved using that solution. For a given image block, the peak‐signal‐to‐noise ratio (PSNR) is used as a quality metric to measure the imperceptibility for the watermarked block. However, the robustness cannot be measured for a single watermark bit using traditional metrics. The proposed method uses the PSNR quality metric to indicate the degree of robustness. Hence, optimum embedding in terms of quality and robustness can be achieved. To demonstrate the effectiveness of the proposed approach, a recent watermarking technique is modified, and then used as the embedding method to be optimised. The Bees algorithm is selected as the optimisation method and the proposed fitness function is applied. Experimental results show that the proposed method provides enhanced imperceptibility and robustness under different attacks.

This paper presents a systematic methodology for exploring possible processor arrays of scalable radix 4 modular Montgomery multiplication algorithm. In this methodology, the algorithm is first expressed as a regular iterative expression, then the algorithm data dependence graph and a suitable affine scheduling function are obtained. Four possible processor arrays are obtained and analyzed in terms of speed, area, and power consumption. To reduce power consumption, we applied low power techniques for reducing the glitches and the Expected Switching Activity (ESA) of high fan-out signals in our processor array architectures. The resulting processor arrays are compared to other efficient ones in terms of area, speed, and power consumption.