Switched-capacitor converters (SCCs) are transcribed as ladder diagrams and are analyzed at different complexity levels: (1) ideal SCC with no load; (2) SCC with finite load and infinite output capacitor; and (3) SCC with finite load and finite output capacitor. In working out the (1/2)X 2N-phase interleaving SCC, the current handling capability of an IC fabrication process is introduced. A SCC, under specific conditions, with unity efficiency is also identified.

A 13.56 MHz wireless power receiver with a reconfigurable resonant regulating (R3) rectifier for implantable medical devices is presented. The receiver adopts the 0X/1X dual-mode modulation and achieves voltage rectification and regulation in one stage. The PWM controller consists of a ramp generator and a Type-II compensator. Hybrid on/off-delay compensation with analog Vdd-sensing and digital multiple pulsing blocking reduces the delay of the active-diode path. Embedded level-shift drivers adaptively provide high voltage to turn off the high-side PMOS active diodes with the mode signal, and they can be decoupled from driving the power PMOS transistors, thus enhancing the overall efficiency. Measurement results show steady delivery of 5V at a load of 400Ω and stable load transients between 1mA to 20mA. The measured maximum power conversion efficiency (PCE) is 92% for a load resistance of 167Ω and the load resistance can be as large as 10kΩ.

Load shift keying (LSK) is commonly used in wireless power transfer (WPT) systems for backscattering information from the receiver back to the transmitter. However, when the coupling coefficient (k) between the coupling coils falls below a threshold value (kDF), the demodulated LSK data can unexpectedly flip from '1' to '0' and '0' to '1'. This phenomenon is referred to as coupling-dependent data flipping (CDDF). This research investigates the factors that lead to CDDF in series-series resonant WPT systems, by taking into account of parasitic parameters of the coupled link and validates the analysis through SPICE simulations. To mitigate CDDF, we propose a carrier-frequency auto-tuning scheme that is also verified by simulation results.

A fully-integrated reconfigurable switched-capacitor converter (SCC) that achieves very low voltage conversion ratios (1/4X, 1/5X and 1/6X) in a 65nm CMOS process is presented. It has three topological phases, and the SCC achieves minimum output resistance for every topology. An analysis is proposed to optimize the system efficiency with the consideration of charge redistribution loss, conduction loss, gate drive loss and bottomplate parasitic loss.

This paper presents a 13.56MHz active rectifier used in a wireless power transfer system for implantable medical devices that employs digital-to-time converters in replacing analog comparators to generate delay-compensated gate control signals for the power transistors. The low-power digital controller employs a successive approximation register (SAR) to generate digital codes for delay compensation, achieving zero-voltage switching and eliminating reverse conduction loss. Fabricated in a standard 65nm CMOS process, the proposed rectifier has an active area of 0.02mm2. The quiescent power is$13.6\mu $W, 15 times lower than the traditional design. The power transfer efficiency is maintained above 90% from 3mW to 40mW with maximum efficiency of 95% at 16mW. Under light load condition, the proposed design achieves more than 20% efficiency enhancement compared to the rectifier without delay compensation.

A 13.56-MHz wireless power transfer (WPT) system with fully integrated transmitter (TX) and receiver (RX) chips is presented. The receiver’s output voltage is locally regulated using a linear current-sink-based regulator, while global power regulation is achieved at the transmitter through a hybrid control strategy that combines constant off-time and hysteretic control for a reconfigurable power amplifier. Synchronized load-shift keying at the receiver improves the relative change in the primary current of the transmitter by >15%. The adaptive digitally controlled active rectifier achieves a voltage conversion ratio (VCR) and power conversion efficiency (PCE) of 0.92 and 92.4%, respectively, for a 200 Ω load resistance. The end-to-end efficiency is improved by 25% at heavy load and 14% at light load by enabling TXglobal power regulation. Both TXand RXchips were fabricated in the BCDlite 180 nm process with 1.8 V/5 V devices. This system achieves a greater operating distance, higher output power, and faster load-transient response while significantly reducing circuit and system design complexity.

In this research, we introduce a hybrid power converter for point-of-load (PoL) applications. By separating the DC-DC converter into two stages, this hybrid converter achieves a voltage conversion ratio of D2/2. Therefore, 5V power transistors can be used in the main current path, which significantly increases efficiency. An adaptive dead-time control and an anti-shoot-through buffer are proposed to further enhance efficiency. With VIN=24V and VOUT=1V, this converter achieves a peak efficiency of 94.5% at 1A output.

The secondary stage of a wireless power transfer system with a series-resonant circuit driving a rectifier load is analyzed in the time-domain. Depending on the load current, the inductor current may operate in continuous, boundary or discontinuous conduction modes (CCM, BCM, DCM). Analytic solutions are derived and confirmed by SPICE simulation and measurement results.

This paper presents a wireless power transfer (WPT) receiver with an adaptive digitally-controlled on-off delay-compensated active rectifier for high-current biomedical implants. High efficiency is achieved by using adaptive digital techniques to compensate for turn-on and turn-off delays, reduce reverse current, and eliminate multiple pulsing. The adaptive scheme improves voltage conversion ratio (VCR) and power conversion efficiency (PCE) at different PVT corners. The generation of the optimal delay compensation current is 1.5 times faster than published works. The proposed design is implemented with 0.18 μm CMOS process. The measured maximum VCR is 0.978 for a 2 kΩ load resistance, and the maximum PCE is 92.2% for a 200 Ω load resistance.

This paper proposes a D2buck converter that achieves higher efficiency than the double-step-down (DSD) converter driving medium load current. It also minimizes undershoot and recovery time of load transient response. The D2buck converter consists of two buck converters in cascade, with the first handling high input voltage and low input current, and the second using low-voltage power switches to enhance efficiency. By implementing a sawtooth generator with well-defined thresholds, the undershoot detector realizes both delay-insensitive response and adaptive on-time extension during load transient. This work is designed in a 180nm BCD process. The first stage converts 24V to 4V, and the second stage converts 4V to 1V. For a load increase from 0.1A to 1.1A with an edge time of 20ns, the worst-case undershoot was better than 15%, and the recovery time was 2.7µs. The simulated peak efficiency was 91.9% with the load current ranging from 0.1A to 4A.

A systematic design technique of flexible tertiary coil in a wireless power transfer (WPT) system for back telemetry detection is presented. The detection (tertiary) coil is co-planar with the primary coil and receives the backscattered load shift keying (LSK) data from the secondary stage. Tertiary coil parameters such as the number of turns, compensation capacitance, and quality factor are determined to maximize the link gain and the end-to-end (E2E) efficiency. The analysis is validated through SPICE simulations and measurements. A novel area-saving inner-tertiary coil is further proposed and critically compared with traditional outer-tertiary coil. The RF electromagnetic radiation or Specific Absorption Rate (SAR) value of the coils was evaluated for possible health hazards using 3D head models and ANSYS/HFSS finite element software. In comparison to a heuristic outer-tertiary coil design, the primary-secondary (operating) distance is improved by 50%, from 12 mm to 18 mm. At an operating distance of 15 mm, the link gain and E2E efficiency are improved by ~207% and ~18%, respectively.

A self-clocked unified voltage-and-frequency regulator (UVFR) is proposed to provide a highly correlated voltage-and-clock pair and to guarantee error-free operation of an arbitrary in-order executed digital load. Built on a digital low-dropout regulator (D-LDR), the unified control loop is highly synthesizable and adaptively clocked to achieve both fast transient response and low quiescent current. Replica frequency-locked loops (FLLs) and hysteresis switching logic (HSL) are employed to compensate for the built-in offset of conventional beat-frequency (BF) quantization and provide calibration-free regulation to tolerate global and random variations. Fabricated in a 65-nm CMOS process, the proposed UVFR reduced the voltage undershoot by 25%, reduced the steady-state offset by 84%, and achieved a 5.9X wider adaptive clocking range compared to the baseline with the help of our proposed replica FLLs and HSL.

A 16-bit on-chip embedded encryption system built upon eFUSE, cipher, hash functions, and EDCs for optical nerve stimulation is presented. The foundry-provided eFUSE IP is modified with a one-shot block to support wireless power transfer operation by mitigating the supply voltage drop problem during sensing to avoid subsequent resetting. Novel logic gate-based auxiliary circuit facilitates different sensing and programming modes in eFUSE. A 128-bit cipher is reduced to 16 bits with cascade structure using the proposed divide-and-conquer algorithm, keeping the cipher strength constant. The developed resource sharing technique reduces the area and the power consumption of the ciper circuits by 2.7 times and 5.1 times, respectively. The whole system with the optical nerve simulator is fabricated with 0.18$\mu$m BCDlite process, and measurement results show the correct encryption operation when powered by wirelessly transferred power.

A detection (tertiary) coil co-planar with the transmitter coil receives and decodes backscattered data from the receiver using load shift keying (LSK). Tertiary coil parameters such as the number of turns, compensation capacitance and quality factor are studied for maximizing voltage gain and end-to-end efficiency through novel analytical modelling, SPICE simulations and measurement results. A novel “inside-tertiary coil structure” is suggested to save the overall coil area, and two variations are discussed. Voltage gain and efficiency are improved by ~197% and ~15%, respectively, at a transmitter-receiver distance of15 mm. Design strategy improves the operating distance of implant by 50%, from 12 mm to 18 mm.

This paper presents a partitioning scheme based on Fiduccia-Mattheyses (FM) Algorithm that targets at designing fully synthesizable spatially distributed digital low-dropout regulators (D-DLDRs) to power up a large digital system. Modeling methods of DLDRs are reviewed and applied to analyze dual and multiple distributed DLDRs. The analysis is confirmed by simulation results and suggests the advantages of using distributed DLDRs over stand-alone DLDRs.

With the advancement of technology, the size of transistors and the distance between them are reducing rapidly. Therefore, the critical charge of sensitive nodes is reducing, making SRAM cells, used for aerospace applications, more vulnerable to soft-error. If a radiation particle strikes a sensitive node of the standard 6T SRAM cell, the stored data in the cell are flipped, causing a single-event upset (SEU). Therefore, in this paper, a Soft-Error-Aware Read-Stability-Enhanced Low-Power 12T (SARP12T) SRAM cell is proposed to mitigate SEUs. To analyze the relative performance of SARP12T, it is compared with other recently published soft-error-aware SRAM cells, QUCCE12T, QUATRO12T, RHD12T, RHPD12T and RSP14T. All the sensitive nodes of SARP12T can regain their data even if the node values are flipped due to a radiation strike. Furthermore, SARP12T can recover from the effect of single-event multi-node upsets (SEMNUs) induced at its storage node-pair. Along with these advantages, the proposed cell exhibits the highest read stability, as the ‘0’-storing storage node, which is directly accessed by the bitline during read operation, can recover from any upset. Furthermore, SARP12T consumes the least hold power. SARP12T also exhibits higher write ability and shorter write delay than most of the comparison cells. All these improvements in the proposed cell are obtained by exhibiting only a slightly longer read delay and consuming slightly higher read and write energy.

Class-D half-bridge power amplifiers (PA) are used to drive the primary coil of a coupled wireless power transfer (WPT) system. We analyze the primary inductor current of cases such as off-resonant operation, overtuned- and undertuned-capacitor operation, and effects due to finite rise and fall times. We also analyze the case with off-resonant Zero Voltage Switching (ZVS) tank. SPICE simulations validate all the analytical calculations with errors smaller than 2%.

A 6.78 MHz single-stage transmitter (TX) using a reconfigurable regulating class-D power amplifier (PA) for wireless power transfer (WPT) applications is presented. Based on a 3-mode modulation scheme, the TX achieves power regulation and transmission with only one power stage. A discontinuous-conduction-mode (DCM) zero-voltage switching (ZVS) scheme is adopted to reduce switching loss. A control loop is set to regulate the output voltage of the WPT receiver (RX) by automatically adjusting the transmitting power. With dual-loop control and a proportional-integral (PI) compensation scheme, the loop achieves tight regulation and fast response. The controller is implemented digitally to benefit from the AirFuel®embedded Bluetooth communication link. The PA was fabricated with a high-voltage 0.35 μm CMOS process, and the digital controller with a standard 0.35 μm CMOS process, respectively. Measurement results show that the output voltage of the RX was correctly regulated to 11.7 V under a load change of 50mA to 500mA, and the WPT system could deliver a maximum power of 7.3 W to the RX over a distance of 4.0 cm, and achieved TX to RX peak efficiency of 57.3%.

To achieve improved speed of operation, a higher integration density and lower power dissipation, transistors are being scaled aggressively. This trend has reduced the critical charge of sensitive nodes. As a result, SRAM cells used in the high radiation environment of aerospace have become highly vulnerable to soft errors. In this paper, we propose a soft-error-aware 14T (SEA14T) SRAM cell for aerospace applications. The performance of the proposed cell is assessed by comparing it with other radiation-hardened SRAM cells like QUCCE12T, WE-QUATRO, RHM12T, RHD12T, RSP14T and RHBD14T. The proposed cell can fully recover from a single-event upset, of any strength and polarity, induced at all the sensitive nodes. Simulation results also show that SEA14T can fully recover from a multi-node upset induced at the internal node-pair. The proposed cell exhibits 1.06×/ 1.08×/ 1.36× shorter read delay than QUCCE12T/ WE-QUATRO/ RHBD14T and 1.03×/ 1.09×/ 1.12×/ 1.15×/ 1.17× shorter write delay than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. It also shows 1.33×/ 1.6×/ 2.4× higher read stability than QUCCE12T/ WE-QUATRO/ RHBD14T and 1.13×/ 1.32×/ 1.37×/ 1.42×/ 1.5× higher write ability than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. Furthermore, the proposed cell consumes 2.31×/ 2.42×/ 2.55×/ 3.04× lower hold power than RHD12T/ RSP14T/ WE-QUATRO/ QUCCE12T @ VDD= 1 V. All these improvements are achieved at the cost of a slightly larger area overhead.

With aggressive scaling of transistor size and supply voltage, the critical charge of the sensitive nodes is reducing rapidly. As a result, when these deep submicron devices are used in memory cells in the space environment, single-event upsets (SEUs), also known as soft-errors, pose a great threat to the reliability of the cells. To mitigate the effects of SEUs, we propose a soft-error-immune read-stability-improved (SIRI) SRAM cell. To assess the performance of the proposed cell, it is compared with other soft-error-immune SRAM cells, namely, QUCCE12T, WE-QUATRO, RHPD12T, RHBD14T and RSP14T. Simulation results confirm that the detrimental effects of SEUs do not alter the state of SIRI as all the sensitive nodes can reattain their initial states after being impacted by an SEU. The cell can also recover from single-event multi-node upsets (SEMNUs) that occur at its storage node-pair. Moreover, the storage nodes of the proposed cell are isolated from the bitlines during read operation. Hence, it exhibits the highest read stability. The write ability and write delay of SIRI are also superior to those of the majority of the comparison cells, and it consumes much lower hold power than many of the conventional SRAM cells. All these improvements are brought about only at the expense of a slightly longer read delay.

This summary presents a fully-integrated wireless charger to achieve high efficiency with low cost and volume. The charger realizes power rectification, voltage regulation and CCCV charging in one power stage only. A bootstrapping technique is also designed for on-chip integration of the bootstrap capacitors. A chip prototype was fabricated in a standard 0.35μm CMOS process with a die area of 8mm2. The charger achieves peak efficiency of 92.3% and 91.4% when the charging currents are 1A and 1.5A, respectively.

A class-D power amplifier (PA) powering a pair of resonant coils is studied. Time-domain analysis of the primary and the secondary sections inductor current with series-series (SS) and series-parallel (SP) resonance are derived, with either resistor or rectifier loads. Both the ripple and rectified output voltage of the secondary section are analyzed. Results are validated through extensive SPICE simulations. Analytical and simulated results are matched with better than 90% accuracy.

This research studies the effect of a starving resistor in various pre-driver schemes for shoot-through loss reduction in the buffer of an integrated DC-DC converter and explores how the efficiency is affected. The starving resistor (Bidirectional delay element) reduces the short circuit current of an inverter by developing time skewed gate driving signals for the driven stage NMOS and PMOS inside a buffer. The starving resistor scheme enhances the efficiency if it is inside the buffer of a switch, but is not as efficient if it is inside the buffer of an active diode. The efficiency of the buffer can be further enhanced by adding delay generator schemes within a buffer. Results are validated via extensive SPICE simulations.

A transient-enhanced output-capacitor-free low-dropout regulator (LDR) based on dynamic Miller compensation (DMC) is presented in this brief. By utilizing different Miller capacitors to compensate the LDR at different load ranges, the proposed DMC technique can extend the loop bandwidth and enhance the transient performances. The DMC scheme is simple and effective. A proof-of-concept LDR with DMC is designed in a 0.18-μm CMOS process. It has a 100-mA maximum load capability with a quiescent current of 8.5 μA. Measurement results show that the output undershoot/overshoot and recovery time of the proposed LDR with DMC are only 38 mV/0.4 μs and 37 mV/1.22 μs when the load current changes between 100 μA and 100 mA, respectively, whereas they are 45 mV/1.3 μs and 200 mV/4.97 μs without DMC. Line transient responses are also significantly improved by the DMC technique.

A fully integrated single-input dual-output switched-capacitor converter with dynamic power-cell allocation for application processors is presented in this summary. The power cells can be dynamically allocated according to the loads, and the efficiency is improved by 4.8%. A dual-path voltage-control oscillator (VCO) that works independently of the power-cell allocation is proposed to achieve a fast and stable regulation loop. The converter achieved peak efficiency of 83.3% and maximum combined load-currents of 100mA while maintaining minimized cross regulation.

A switched-capacitor DC-DC converter with a low output voltage ripple and high efficiency is presented in this summary. To achieve a wide input and output voltage range, a 3-clock-phase operation is proposed to achieve 6 voltage conversion ratios (VCRs) with only two discrete flying capacitors. A digital ripple reduction scheme is utilized to achieve up to four times reduction in output voltage ripple. The digital design also improves the design flexibility. The converter can deliver a 250mW maximum power to a wide output range of 0.5 V to 3 V with an input range of 1.6 V to 3.3 V, and achieves a peak efficiency of 91%.

An ultra-lower-power reconfigurable voltage detector for indoor solar energy harvester is presented. The voltage detector monitors the solar cell voltage and sends out a flag signal if the solar cell voltage surpasses the triggering threshold of the detector. Instead of using a traditional dynamic comparator, this design is based on a power-on-reset (POR) circuit. A POR circuit has ultra-low quiescent loss and a fixed triggering threshold, which is determined by its topology and process. Our improvement is to use a feedback loop that allows the triggering threshold to be reconfigurable. The average quiescent loss of this POR voltage detector circuit is 2.774nW. Process and temperature variations can also be compensated by the feedback loop. The energy harvesting system is designed with a 0.18 p,m CMOS process. Equipped with the proposed voltage detector, the whole system achieves a 93.21% peak efficiency at 200μW input power.

A wireless power receiver using a 3-level reconfigurable resonant regulating (R3) rectifier is presented in this summary. The receiver improves power conversion efficiency and reduces die area and off-chip components by achieving power conversion and voltage regulation in one stage, using only 4 on-chip power switches and 1 off-chip capacitor. The receiver regulates the output voltage at 5 V and delivers a maximum power of 6 W. It was fabricated in a standard 0.35 μm CMOS process with a die area of 4.77 mm2, and the measured peak efficiency reaches 92.2%.

A 13.56 MHz 64.8 mW fully-integrated CMOS active rectifier for biomedical wireless power transfer system is presented in this summary. It employs an adaptive on/off delay compensation technique to accurately compensate for the circuit delays despite PVT variations and mismatches. With an AC input that ranges from 1.8 V to 3.6 V, the measured voltage conversion ratio is higher than 90% and the measured power conversion efficiency is higher than 89.1% for a load resistor of 500 Ω.

A 13.56 MHz wireless power receiver designed with standard CMOS 0.35 μm process used for implantable medical devices (IMDs) is presented. By adopting a one-stage 0X/1X reconfigurable resonant regulating (R3) rectifier, the proposed architecture inherently avoids system voltage conversion ratio (VCR) variation and power conversion efficiency (PCE) degradation problems and thus widens the operation region dramatically. Effects due to the parameters of the coil on the overall system performance are studied and a 50 nH inductor is used in the secondary side to achieve fully on-chip implementation. Based on a synchronized PWM control scheme, the proposed rectifier achieves voltage regulation with only 4 power transistors and 2 gate-driving buffers, which enables compact design and efficient rectification. Meanwhile, the output capacitor can be reduced to 200 nF, while the output voltage is regulated at 3.6 V with less than 100 mV ripple. Simulation results show that the maximum output power is 103.5 mW with efficiency of 91.7%.

In this paper, we study the stability conditions for hybrid supply modulators (HSMs). We investigate the limitations of the Nyquist stability criterion, the standard technique of evaluating the stability of a linear time-invariant (LTI) system, when applied to HSMs, and demonstrate that it cannot assess the stability of two recent HSMs. To overcome these limitations, a general large-signal stability condition is suggested, which can be regarded as a natural extension of the stability condition used for hysteretic-controlled HSMs. It successfully explains the stability of these two recent HSMs. Based on the new stability condition, we propose two control methods for HSMs that couple the input signal to the switching loop directly, and verify their stability by timedomain simulation results. The proposed stability condition opens door for constructing new HSMs.

A dual-mode Single-Input-Dual-Output converter with fully digital time-based Maximum-Power-Point-Tracking is presented to efficiently harvest indoor solar energy. The converter uses only three power switches to minimize the chip area and reduce the switching power loss, and dual-mode to accommodate the power imbalance between the Photovoltaic (PV) cell supply and the load requirement. Under sufficient illumination condition such that the PV cell provides more power than needed by the load, the system will operate in light-load mode, supplying sufficient energy to the load and storing the surplus energy to battery. If the environment is under-illuminated, the system will switch to heavy-load mode, and the stored energy is extracted from the battery to supply load together with the PV cell. The power converter is designed with 0.18μm CMOS process. From the simulation results, a peak power conversion efficiency of 91.23% is achieved.

This paper presents a generic model that links the compensation techniques used in two-stage amplifiers to the structures of three-stage amplifiers. Many previous designs can be derived from this model, and new three-stage amplifiers can potentially be constructed. A novel three-stage amplifier based on this generic model is proposed. Simulation results show that the proposed design outperforms many recent designs.

In RF energy harvesting for wireless sensor network, due to the variation of the available RF power for individual node sensor, the conventional Dickson rectifier could not achieve the optimal harvesting efficiency in a wide available power range. In this work, a novel reconfigurable rectifier with adjustable conversion ratio is proposed without changing matching network. Based on this, a WLAN (2.4 GHz) RF energy harvesting system is proposed with the maximum power point tracking (MPPT). The entire system is implemented in an 180nm CMOS process. Post-layout HSPICE simulation results show that with MPPT, the reconfigurable rectifier achieves a high energy harvesting efficiency for a wide available power range and is configured with 3.3x response time reduction when compared with the existing reconfigurable rectifier to cater for the frequent changing RF power.

A low-dropout regulator (LDR) using a matching-enhanced error amplifier (ME-EA) and a multi-threshold-controlled unity-gain buffer (MTC-UGB) is proposed in this work. With the majority of transistors being high-voltage devices of the process, the regulator tolerates a high in put voltage range, which alleviates the reliability concern caused by low-voltage transistors. The ME-EA allows for tight line and load regulations. The MTC-UGB, by using low-voltage input transistors with locally regulated terminal voltage, enables large loop bandwidth and fast load transient responses without using compensation capacitor or large ESR of the output capacitor for compensation. Fabricated in a 0.13μm CMOS process, the proposed LDR occupies 0.035 mm2of active area and consumes 18 μA of quiescent current and achieves 6 mV of voltage dip for 150 mA of load transient.

A low-power low-noise chopper operational amplifier for biosensor applications is proposed. It employs a simple ripple suppression method using a band-pass amplifier. The input referred noise is only 43nV/rtHz. Fabricated in a 130nm standard CMOS process, it occupies a chip area of 0.28mm2and consumes 33ßA from a 1.2V supply.

This paper presents a high-frequency half-bridge driver for enhancement-mode GaN-on-Si HEMTs with digital dead-time correction (DDTC) to optimize the dead-time. Due to the lateral HEMT structure, dead-time optimization is essential for synchronous driving. It helps reducing the reverse conduction loss to enhance the efficiency and reliability. The DDTC scheme achieves instant sensing with all-digital feedback control to adjust the dead-times dynamically according to load changes. The proposed half-bridge driver for GaN HEMTs is designed in 0.35μm HV CMOS technology. Simulation results show that the DDTC scheme is able to reduce the dead-times to within 2ns and the efficiency is improved by 4.9% compared to the fixed dead-time scheme in a 12V-1.2V conversion with a 12A load current.

In RF energy harvesting, due to the variation of the available RF power, the conventional Dickson rectifier could not achieve the optimal harvesting efficiency in a wide available power range. To tackle this issue, in this work, a reconfigurable rectifier with adjustable conversion ratio is proposed without affecting the matching with the antenna under different configurations. Based on this, a UHF (900 MHz) energy harvesting system with maximum power point tracking (MPPT) is proposed. The system is implemented using TSMC 65 nm CMOS process. Post-layout HSPICE simulation is performed for verification. With the MPPT, the reconfigurable rectifier is always configured to achieve the maximum efficiency.

This paper presents a circuit-oriented geometrical approach in predicting subharmonic oscillation of DC-DC converters with voltage-mode control. It is based on straightforward graphical analysis of the operation of the converter without using sophisticated mathematical tools. The critical condition of subharmonic oscillation of the buck converter is derived, which is shown to be related to the slope of the output of the compensator Veaat the trip point rather than the amplitude of the ripple voltage of Vea. The proposed analysis is verified for converters with a proportional or a Type-III compensator.

To treat retinal degenerative diseases, a transcorneal electrical stimulation-based system is proposed which consists of an in vivo eye implant and an in vitro control device. The eye implant is wirelessly powered and controlled by the in vitro device to generate the required bi-phase current pattern for the transcorneal stimulation with an amplitude range of 5μA~320μA, a frequency range of 10Hz~160Hz and a duty ratio range of 2.5%~20%. Only one pair of coils is used for both the power link and the bi-directional data link. Except the secondary coil, the eye implant is fully integrated on chip and fabricated using UMC 0.13μm CMOS process with a size of 1.5mm by 1.5mm. The secondary coil is tiny and fabricated on a PCB with an outer diameter of only 4.4mm. After packaging with biocompatible silicone, the whole implant has a dimension of 6mm diameter with a thickness of less than 1mm. The whole device can be put on the sclera and beneath the eye's conjunctiva. Measurement results verify the system's functionality and demonstrate the performance.

A low-dropout regulator (LDR) using an ultra-fast error amplifier (EA) and ultra-fast unity-gain buffer (UGB) is proposed in this paper. By inserting a UGB between the EA and the inverting second stage, the non-dominant poles are pushed to high frequencies to achieve large loading capability and wide loop bandwidth with good stability. High power supply rejection (PSR) up to very high frequencies is hence achieved. Moreover, transient-enhancement techniques employed by the EA and UGB enable very fast load transient responses. The proposed LDR was designed in a 0.13μm mixed-mode CMOS process. Simulation results show that the quiescent current is 4μA and it achieves 7mV voltage dip for a load current step of 400mA with 1ns edge times. The PSR for all load range are better than -28dB at 10MHz and -9dB at 50MHz, respectively.

In this work, an output-capacitor-free (OCF) low-dropout regulator (LDR) employing fully differential input stage is proposed. By using a fully differential input stage, the proposed OCF LDR is able to improve the transient responses without the help of any additional transient boosting circuitry. This design is stabilized with a 0.37pF compensation capacitor. It is able to provide a maximum load current of 100mA at 0.7V to 1.2V supply with less than 200mV dropout voltage. Implemented in 0.13μm CMOS technology, it consumes a quiescent current of 4μA and occupies an active area of 0.0132mm2.

A novel single-inductor dual-input dual-output dc-dc converter with pulse width modulation control is proposed for a solar energy harvesting system. The first input of the converter is from photovoltaic (PV) cells and the second input is a rechargeable battery. Apart from the conventional role of providing a regulated output voltage to power the loading circuits, the converter also clamps the PV cells' voltage to the maximum power point value to maximize efficiency. When the PV cells harvest more power than the load, the surplus energy is used to charge the rechargeable battery. When the PV cells cannot harvest sufficient power, the converter schedules the PV cells and the battery to power the load together. A test chip was fabricated using a 0.35-μm CMOS process and measured to verify the operation of the proposed dc-dc converter and to demonstrate the power transfer efficiency of the solar power management system.

This paper proposes a High-Side (HS) NMOS power switch and bootstrap driver with DCM charging phase extension for high-frequency fully-integrated converters with 1.2V supply voltage. The conventional bootstrap diode is replaced by a self-synchronized switch and the efficiency loss and operation failure at DCM is prevented by an extra charging phase. Simulation at 100MHz with UMC 0.13μm process shows that the optimum efficiency is driven 2% higher with significant power loss reduction by the proposed design compared to a conventional converter under similar operation conditions. 20% power stage area is saved by the dual NMOS structure compared to the conventional converter with PMOS and NMOS switches.

An output-capacitor-free adaptively biased low-dropout regulator with transient enhancement (ABTE LDR) is proposed. Techniques of Q-reduction compensation, adaptive biasing, and transient enhancement achieve low-voltage high-precision regulation with low quiescent current consumption while significantly improving the line and load transient responses and power supply rejections. The features of the ABTE LDR are experimentally verified by a 0.35-μm CMOS prototype.

This paper presents an output-capacitor-free adaptively biased low-dropout regulator with sub-threshold undershoot-reduction (ABSTUR LDR) for SoC power management applications. Techniques of Q-reduction compensation and adaptive biasing (AB) are employed to achieve low-voltage high-recision regulation with enhanced loop bandwidth while maintaining low quiescent current and high current efficiency. A symmetrically matched current-voltage mirror is used to implement the AB scheme, enabling an accurate load current sensing even with the pass transistor working in the linear region that is beneficial for chip-area saving. The dedicated STUR circuit, which is low-voltage compatible and consumes very low current in the steady state, is inserted to momentarily increase the gate discharging current of the pass transistor when the LDR output has a large undershoot due to a large step up of the load current. Features of the proposed ABSTUR LDR are experimentally verified by a prototype fabricated in a standard 0.35-μm CMOS process.

Charge balance law based on conservation of charge is stated and employed to analyze charge pumps. For micro-power on-chip implementations, both the positive-plate and the negative-plate parasitic capacitors have to be considered. A first iteration approximation analysis is proposed to analyze charge pumps with parasitic capacitors. Using a 0.35µm CMOS process, 8X linear, Fibonacci and exponential charge pumps are designed and their performances are compared and confirmed by simulations.

In this work, we present a vibration-based energy scavenging system based on piezoelectric conversion for micropower applications. A novel maximum power point (MPP) tracking scheme is proposed to harvest the maximum power from the vibration system. A time-multiplexing mechanism is employed to perform energy harvesting and MPP tracking alternately. In the MPP tracking mode, a voltage reference that represents the optimal output voltage at the MPP is generated. A control unit then uses this reference to track the system operation around the MPP. The proposed system is capable of self-starting up without the help of an energy buffer. As a result, it is suitable for battery-less applications or when the energy buffer is completely drained. This tracking scheme has very small power overhead and is simple to implement in VLSI. Hence, it is especially applicable for micropower systems. The entire design was fabricated in a 0.35-μ m CMOS process. Experimental results verified the proposed MPP tracking scheme and demonstrated the system operation. Measurement results show that the power harvesting efficiency of the electrical circuitry is higher than 90%.

Energy harvesting is becoming more and more popular for micro-power applications where the environmental energy is used to power up the systems. In order to prolong the device lifetime and guarantee the system operation, the harvested power from the energy transducer to supply the system load should be maximized. This paper reviews different techniques and solutions to maximize the harvested power. Different environmental energy sources and the characteristics of the corresponding energy transducers are discussed. Algorithms to detect and track the maximum power point (MPP) of the energy transducer are summarized. Different power management unit (PMU) designs to execute MPP tracking (MPPT) algorithms are presented.

Three freewheel duration adjustment circuits based on the principle of phase-lock loop are proposed to enhance the efficiency of single-inductor dual-output (SI-DO) switching converters. The SI-DO converter works in pseudo-continuous conduction mode and uses charge control with a single-charge successive-discharge scheme. The first circuit defines a constant freewheel time (TFW); the second uses the ratio of charging and discharging currents to define TFW/T; and the third adjusts TFW/T according to the load current. The integrated converter is designed using a 0.35μ CMOS process.

Conventional design methodologies for EPC RFID tags focused on minimizing the power consumption of each building block to obtain the maximum achievable communication distance. In this work, we analyze different operation states of the RFID tag and their corresponding power consumption characteristics to identify the limiting factor that dictates the communication distance. Based on the analysis, we propose two approaches to extend the communication distance: (1) shaping the load power to track the unbalanced input power to the tag; (2) scheduling the load to average out the large burst power consumption. Simulation results show that the sensitivity can be improved by 1.8dB.

A single inductor dual input dual output (SIDIDO) DC-DC converter is proposed for solar energy harvesting applications. The converter supports hybrid power supplies from both the photovoltaic (PV) cells and the rechargeable battery. The proposed DC-DC converter provides a regulated output voltage to power the load as well as clamps the input voltage from the PV cells to the maximum power point (MPP) value so as to extract the maximum power from the PV cells. At the same time, one of the dual outputs is used to charge up a rechargeable battery when the PV cells output power is larger than the load. A simple bandband control is proposed for controlling the power flow between different sources and destination under different power operation modes. Extensive simulations were carried out to verify the operation and demonstrate the power transfer efficiency of the proposed DC-DC converter.

A series of bandgap references (BGRs) using a self-biased symmetrically matched current-voltage mirror (SM CVM) in reducing systematic offset, thus achieving an excellent line regulation, is presented. By replacing the operational amplifier with a CVM in the feedback loop, current consumption is much reduced. An SM buffer stage that is capable of driving a resistive load with minor degradation in temperature coefficient (TC) and line regulation is also presented. The technique is extended to design a sub-1-V BGR with a TC-cancellation output buffer. All circuits are designed using a 0.35- CMOS process, and experimental results are presented, confirming the analysis.

An inductor-less maximum power point tracker was designed for light energy harvesting systems. We target at systems under different lighting environments and sometimes the solar cell voltage may be low. A charge pump is used to convert the voltage to a higher value. At the same time, the control circuit tunes the charge pump switching frequency to track the system maximum output power point. The design was fabricated and measured to verify the system operation.

An integrated voltage-mode boost converter that starts up at 0.9 V is successfully implemented in a standard 3.3/5 V 0.6 mum CMOS process with Vtn=0.7 V and |Vtp|=0.8 V. The special features are: (1) a near-threshold soft-start circuit that keeps maximum in-rush current under control; (2) a slew rate enhanced error amplifier that achieves stable response over a wide range of supply voltage; and (3) a capacitor multiplier in implementing the compensation capacitor that reduces die area. Maximum efficiency of 93% is achieved at an output power of 260 mW.

A high-precision low-voltage low dropout regulator (LDR) using adaptive biasing to extend the loop bandwidth is proposed for system-on-chip power management applications. The multi-stage output-capacitor-free LDR is stabilized by miller compensation and Q-reduction technique to reduce the requirement of minimum load current. By using direct current feedback from a simple current mirror, the adaptively-biased LDR achieves higher loop bandwidth, faster load and line transient responses, higher power supply rejection and lower output impedance. The load and line regulations are also improved. Designed in a standard 0.35µm CMOS technology (Vtn≈ 0.52V and Vtp≈ −0.72V ), the 1.2V input 1.0V output LDR requires a minimum load current of 50µA and delivers a maximum current of 100mA. Both theoretical analysis and simulation results are presented to demonstrate the advantages of the proposed LDR.

A single inductor dual input dual output (SIDIDO) DC-DC converter is proposed for solar energy harvesting applications. The converter supports hybrid power supplies from both the photovoltaic (PV) cells and the rechargeable battery. Apart from the conventional role of providing a regulated output voltage to power the load, the proposed DC-DC converter also clamps the input voltage from the PV cells to the maximum power point (MPP) value so as to extract the maximum power from the PV cells. At the same time, one of the dual outputs is used to charge up a rechargeable battery. When the PV cells output power is insufficient for the load, the converter will schedule the PV cells and the battery to power the load together. When the PV cells output power is larger than the load, the surplus PV cells energy is used to charge the rechargeable battery through the converter's second output. Extensive simulations were carried out to verify the operation and demonstrate the power transfer efficiency of the proposed DC-DC converter. Copyright 2009 ACM.

An inductor-less on-chip micro power management system for light energy harvesting applications is presented. We target at wide variety of applications that operate at different lighting environments ranging from strong sunlight to dim indoor lighting where the output voltage from the photovoltaic cells is low. A step-up charge pump is used to directly operate the circuit or to charge a rechargeable battery. The power management system operation is discussed and the control strategy for transferring the maximum output power from the power system is presented. Low power circuit design is proposed for the implementation of the system maximum output power control. The system was implemented using a 0.35-mum CMOS process. The chip was fabricated and measurements were conducted for different lighting conditions to demonstrate the system operation and verify the control strategy.

An integrated single-inductor dual-input dual-output (SI DIDO) boost converter for energy harvesting applications was designed in a 0.35μm CMOS process. It provides two regulated output voltages for the load and the charge storage device, and two sources, the energy harvesting source and the charge storage device, are multiplexed to serve as the input. The implementation has several special features. (1) The input power MUX is driven by an internal charge pump for a larger gate drive to save area. (2) The power stage is implemented with an active diode core to eliminate gate drive circuitry. (3) A 1:7 timeslot scheduling with a fixed peak inductor current is adopted to deliver energy to the two outputs with a large difference in load currents. The proposed converter could operate at 1V with up to 85% efficiency at 200mW.

A batteryless power management unit (PMU) that manages harvested low-level vibration energy from a piezoelectric device for a wireless sensor node is presented. An energy-adaptive maximum power point tracking (EA-MPPT) scheme is proposed that allows the PMU to activate different operation modes according to the available power level. The harvested energy is processed by an ac-dc voltage doubler followed by on-chip charge pumps with variable up/down conversion ratios for higher efficiency. Interleaving technique is employed for the high-power output to reduce both current and voltage ripples. The PMU is designed using a 0.35μm CMOS process, and simulation results are presented to demonstrate its functions.

This paper proposed a vibration driven energy harvesting platform based on piezoelectric material. A new maximum power point tracking (MPPT) method for this platform is also presented. This platform harvests ambient vibration energy as its power source, and is capable of self-starting, and self-powered operation without the need of a battery. The proposed MPPT methodology consumes very little power, and is especially suitable for the environments, where ambient harvested power is very low. System modeling, analysis, and implementation are developed. Simulation results show that the power harvesting efficiency with the proposed MPPT scheme is higher than 90% and the power utilization efficiency of the overall platform is higher than 50%.

A micro solar power management system is presented for energy harvesting applications. An inductor-less solution is proposed which facilitates the system on-chip integration. The authors target at the applications working in different lighting environments ranging from strong sunlight to dim lighting where the output voltage from the photovoltaic (PV) cells is low. A charge pump is used to step up the PV voltage to charge a battery or directly operate the circuit. The solar power system behavior is analyzed and the control strategy is derived in order to achieve maximum power transferred from the PV cells to battery or computation circuit. Simulations for the power management system were carried out to verify the proposed control strategy.

In this work, the design of a mechanical vibration energy scavenging and management system is presented for ultra low power applications. A new maximum power point tracking (MPPT) scheme is proposed for piezoelectric conversion. This scheme consumes very little power and is especially suitable for ultra low power energy harvesting applications. This design is capable of self-starting and self-powered, thus eliminates external battery integration and significantly reduces the system volume. System modeling, analysis, and VLSI implementation were developed. Various simulations were carried out and the simulation results show that the proposed MPPT scheme can achieve an energy harvesting efficiency higher than 90%.

A micro power management system is presented for solar energy harvesting applications. An inductor-less solution is proposed which facilitates on-chip integration of the system. We target at applications working in different lighting environments ranging from strong sunlight to dim indoor lighting where the output voltage from the photovoltaic (PV) cells is low. A charge pump is used to step the PV voltage up to charge a battery or directly operate the circuit. The power management system behavior is theoretically analyzed and the control strategy is derived to transfer maximum power from the PV cells to the battery or the circuit. Circuit design and low power techniques for the maximum output power control are proposed for the system. The system was implemented using 0.35μm CMOS process. With the measured PV cells output characteristics, HSPICE simulations for the power management system were carried out to verify the control strategy and to demonstrate the system operation.

A noninverting flyback converter using an integrated symmetrically-matched self-biased current sensor was fabricated in a 0.35/spl mu/m CMOS process. It operates in pseudo-continuous conduction mode and employs a direct output current control scheme to achieve excellent line transient response. The converter switches at 1MHz with an input of 1.2V to 2V to give an output of 1.5V and delivers 250mA.

A capacitor-less low dropout regulator (LDR) with direct current feedback is proposed. A symmetrically-matched voltage mirror in sensing the load current is employed, and gives excellent line and load regulations. The dynamic biasing results in an LDR with pole-tracking that extends the bandwidth of the loop gain at high load currents. The LDR was fabricated in a 0.35/spl mu/m CMOS process with an active area of 0.11mm/sup 2/, and measurement results corroborated well with both analysis and simulation.

A power management and computation methodology is proposed for ultra-low power energy harvesting applications. An integrated exponential charge pump that accepts an input voltage of around 150mV and provides an unregulated output voltage of more than 1.5V serves as the power supply. To cater with the fluctuated energy source and unregulated power supply, a supply side charge-based computation methodology is proposed, of which the computation activity tracks with the fluctuation of the available energy. The idea is demonstrated in a test chip fabricated using a 0.35 mum technology

A novel charge based computation system is proposed for ultra low power applications based on energy harvesting. An integrated exponential charge pump that accepts an input voltage of around 150mV and provides an unregulated output voltage of more than 1.5V serves as the power supply. To track with the unregulated voltage supply, a supply side charge-based computation methodology is proposed. Charge based control strategy is further derived to efficiently use the harvested energy and to increase the number of computations during a certain time interval. The suggested system and control strategy are demonstrated in a test chip fabricated using a 0.35/spl mu/m technology.

Reversion loss is analyzed in details. A 2/spl times/ cross-coupled charge pump in a 0.35/spl mu/ CMOS process is designed using a gate control strategy that eliminates reversion loss. It switches at 1MHz, delivers a current of 30mA, and reaches an efficiency of 95% for an input voltage of 1V to 1.6V.

A current-mode binary-search sensing scheme for a 4-state one-transistor one-magnetic tunnel junction (1T1MTJ) magneto-resistive random access memory (MRAM) is proposed. By using the switched-current technique, it is able to read data non-destructively with a magneto-resistive (MR) ratio of as low as 5%. The circuit is designed using a 0.18mm CMOS process and the performance is verified by HSPICE. Compared to the parallel sensing approach, the proposed sensing scheme consumes less power and chip area and requires fewer comparison steps. Compared to the serial sensing approach, it allows a shorter read access time while requiring the same number of comparisons.

An integrated boost DC/DC converter that provides two different outputs with a 1.8V input using only one inductor is presented. The converter works in discontinuous conduction mode and employs time division multiplexing in switching the inductor current to the two outputs. Synchronous rectification for high efficiency is implemented. Techniques for current sensing, inductor ringing suppression and controller design are discussed. At an oscillator frequency of 1MHz, the conversion efficiency reaches 90% at 350mW.

An IC controller in a standard 2 /spl mu/m CMOS process implementing the phase-controlled dimmable electronic ballast scheme for compact fluorescent lamps is presented. It features alternate power cycle sensing and closed-loop control for stable change in lamp intensity from full brightness down to 5%.

This paper proposes a novel voltage-control scheme to improve the slow dynamic response of the conventional pulse-width-modulation (PWM) continuous-current-mode (CCM) voltage-programming DC-DC converter. By introducing a high-pass notch filter in the control loop of the conventional converter, the unity gain bandwidth of the loop gain is enhanced and the system Q value is decreased. To demonstrate the improvement in the transient response, voltage-programming PWM CCM DC-DC converters with both the conventional and the proposed control schemes are designed and simulated. Results show that the dynamic response has 10 times improvement.

This paper introduces an alternative structure to implement damping-factor-control frequency compensation for three-stage amplifiers. A theoretical analysis is presented, and experimental results are included. From the experimental results, the new structure provides better phase margin and power supply rejection ratio but higher power consumption and larger chip area are required.

The realization of cochlear filters using switched capacitor biquads is described. This approach is made possible by a new design technique, called charge-differencing (CD), which easily reduces by 25% (or more) the silicon area required to implement very-large-time-constant (VLT) biquads. In this technique, filter time constants are controlled by both the product of two capacitor ratios and the differences of capacitor values, making the capacitor spread ratio very small. The new switched capacitor biquads are also stabilized against operational-amplifier nonideal characteristics, such as input offsets and finite gains, using a two-phase gain- and offset-compensation method.>