Compute-in-memory-based accelerators have gained significant attention due to their promising potential. However, many studies in this area often focus solely on the accelerator's performance without considering the latency and energy consumption associated with external data access. Moreover, many have observed a gap in energy efficiency between the macro and the accelerator levels. Our work addresses this problem by proposing an SRAM CIM-based AI accelerator design that reduces additional memory access and mitigates the overhead associated with external data access. Our results demonstrate that lowering the ratio of total local memory capacity to total CIM macro capacity closes the energy efficiency gap between the macro level and the accelerator level.

Write assists (WAs), such as negative bitline and collapse supply voltage (VDD), can effectively improve the write Vminof static random access memory (SRAM) cells. The energy overhead associated with such assists is considerable due to the switching activities on high capacitive nodes for every write operation. In this brief, a conditional biasing WA with built-in time-based write-margin-tracking is proposed to avoid unnecessary assist for energy saving. The biasing voltage for assisting the write procedure is only adjusted during write failures and remains unchanged for native write-success cells. Compared with conventional WAs, the proposed design can reduce write energy by 29%-34% with a similar area overhead. In addition, silicon measurements have demonstrated that the proposed assist is functional for near-threshold operations and VDDminis reduced to 0.4 V.

With a large number of networked devices deployed in the internet of things (IoT), secure communication has become one of the major concerns. A physical unclonable function (PUF) can provide every chip with a unique fingerprint that is difficult for attackers to hack. Furthermore, the PUF provides a light-weight key generator to enhance the IoT security. In this paper, we present a reliable and highly energy efficient PUF with a dark-bit avoidance mechanism to mitigate reliability issues. The measurement results demonstrate that, when compared with several other designs, the proposed design has a smaller area per bit, a lower bit error rate and higher energy efficiency.

General-purpose graphics processing units (GPGPUs) are gaining popularity. Applications like machine learning and artificial intelligence have been growing rapidly. When hardware complexity increases to meet the computing requirements of the applications, the power efficiency of the hardware becomes an important issue. In this paper, we propose an adaptive power management scheme for GPGPU to enhance power efficiency by proactively detecting the internal activities during runtime and dynamically adjusting the operating frequencies of selected components. The simulation results indicate that, when compared with the baseline approach, the proposed scheme can reduce power consumption by up to 15% with a performance overhead of less than 5% on average.

Leakage power dissipation has become a major problem in advanced process technologies, especially in large SRAM designs. The use of adaptive techniques is a promising approach to decreasing power consumption through dynamic scaling of the supply voltage of integrated circuits. To obtain maximum reduction in leakage power, an adaptive data retention voltage (DRV)-regulating scheme is proposed to achieve substantial saving of SRAM standby power. The proposed design supports DRV operation from the above-threshold to subthreshold regions and self-adapts to process, voltage, and temperature variations by using the proposed DRV monitor. According to the measurement results, the proposed design using 90 nm CMOS technology exhibits maximum leakage savings of 71.5%.

When multiprocessor system-on-chip designs are subjected to aggressive scaling of the processing technology, severe thermal effects will influence the performance, power and reliability of integrated circuits (ICs). Hence, IC designers employ mesh-based transient thermal analysis (MTTA) to effectively predict the variations and distribution of temperatures in a chip during the early stages of IC design. The number of cells used in MTTA tools is decided by the user. However, users are generally unclear about whether the number of cells used for three dimensions is appropriate. An unsuitable number of cells may reduce the analytical performance or cause larger analysis errors in MTTA. Hence, MTTA using an appropriate number of cells can obtain higher analytical performance while maintaining acceptable accuracy. In this paper, we developed a temperature gradient exploration (TGE) method for exploring the appropriate number of cells to use in MTTA. The experimental results showed that the TGE method can find the appropriate number of cells and enhance the analytical performance of MTTA with acceptable accuracy.

This paper presents a novel calibration technique for charge redistribution digital-to-analog converters (DACs). By using the proposed clock-pulse-width calibration, the clock of the DAC is modulated, and the output voltage is effectively modified to enhance the differential-non-linearity (DNL) and integral-non-linearity (INL). By using this method, the measured DNL, and INL have been improved by 61% and 87%, respectively. This calibration is done in few steps, and is aided by a cyclone IV FPGA and an ADC. The DAC has been manufactured in a TSMC 90 nm CMOS process, with a core area of 0.011 mm2. The supply voltage, power consumption, and clock frequency of the IC are 1.2 V, 371 uW, and 8 MHz, respectively.

Nonvolatile static random-access memory (NV-SRAM) is a crucial component type for normally-off computing systems. This work proposes a novel 10T2R resistive random-access memory (ReRAM)-based NV-SRAM controller that is aware of redundant bit writes and considers the conditions of redundant bit writes. When data stored in SRAM cells are the same as the data in ReRAM devices, backup can be skipped. Otherwise, backup is performed. As a result, redundant bit-write conditions indicate that energy can be saved when backing up data. Simulations show that as much as 93% of typical energy requirements can be saved when the high resistive state is larger than 10 MΩ. As long as the probability of redundant bit writes is larger than 25%, backup energy saving can be achieved. The ReRAM chip is manufactured with 90 nm CMOS technology and the ReRAM process of the Industrial Technology Research Institute. This design can be applied to L2 and L3 caches.

A sophisticated SoC chip that incorporates many design modules including 2 ARM-like CPUs, a dynamic voltage and frequency scaling (DVFS) design, a master/slave temperature sensing system, and an on-chip test/debug platform is developed and implemented with TSMC 90 nm technology. Measurement results validate the functions and efficiencies of the whole chip.

Normally-off computing (NoC) is one of promising techniques that benefits microsystems with long sleep time. Because NoC can turn off power to achieve zero power consumption and can activate microsystems instantly. This study proposes a novel resistive random access memory (ReRAM)-based nonvolatile flip-flop (NVFF), fabricated using 90-nm CMOS technology and the ReRAM process of the Industrial Technology Research Institute. The proposed NVFF uses a complementary structure with one-phase store to mitigate limitation on store energy and was verified as the registers in three pipeline stages of a NV multiplier-and-accumulator macro. The proposed ReRAM-based NVFF, compared with the state-of-the-art complementary design, can reduce store energy by 36.4%, restore time by 64.2%, and circuit area by 42.8%. The proposed design was also superior in reducing restoration error (by 9.44%) under hardship condition compared to NVFFs with a single NV device.

Adaptive design is one of the most promising approaches for mitigating the large design margin used by dynamically scaling the supply voltage and frequency of integrated circuits. A low cost and power efficient variation detection circuit is one of the critical components intended to achieve the goal of adaptive control. In this paper, we proposed a pulse-based timing error prediction mechanism that can minimize safety margins with low design overhead. When compared with the conventional canary-based circuit technique, 28.7% power reduction is achieved under 50% data activity. Moreover, an average of 48.3% power reduction is obtained across different process corners at ultra-low voltage regime as compared to the worst case design.

Subthreshold logics and memories are crucial elements in ubiquitous-computing applications. The subthreshold circuits need level converters to communicate with the other circuits that use high supply voltages. However, level conversion from sub-to-super-threshold voltage suffers from weak driving strength and severe process variations. The level conversion may depend on the size or threshold voltage of the transistors. This paper therefore analyzes level converters that can robustly convert subthreshold signals without using ratio-sized or multiple-threshold-voltage transistors. The limit of the subthreshold level conversion is thoroughly analyzed. This study suggests that level converters using current-mirror structures are superior candidates for converting subthreshold signals, according to the analytical and simulation results.

Performance estimation at system-level involves quantitative analysis to allow designers to evaluate alternative architectures before implementation. However, designers must spend a tremendous amount of time in system remodeling for performance estimation for each alternative solution in a huge design space. The effort required for system remodeling prolongs the exploration step. Furthermore, the accuracy and speed of performance analysis affects the effectiveness of architectural exploration. This work presents an architectural performance analysis using a dynamic trace-based method (APDT) to reduce the effort required for system remodeling and the time required to estimate performance during architecture exploration, thereby improving the effectiveness of that exploration. Experimental results demonstrate that the APDT approach is faster than the bus functional-level simulation on CoWare with a minor average deviation.

Growing complexity in system-on-a-chip (SoC) design demands effective approaches to explore various architectures quickly for the target applications. With the common use of intellectual properties (IPs) in SoC and the large amount of data interchanges among IPs, communication architecture significantly affects the system in terms of power and performance. Therefore, designers should carefully plan the communication architecture to meet the power and performance requirements. While repeatedly performing a power optimization under a performance constraint approach N times seems practical for the power and performance co-exploration, the time required to explore such solutions inevitably increases, since there are numerous performance constraints. This paper presents a pseudo-parallel method for bus architecture exploration at the system level (PBAES) to speedup the power and performance of co-exploration time. PBAES can intelligently search interesting portions of the design space to enhance the efficiency of co-exploration, and share the candidate solutions of each to achieve a more rapid overall exploration. The experimental results indicate that PBAES is 1.6 times to 14 times faster than an approach without the pseudo-parallel method with a generated architecture of similar quality.

Level converting flip-flops (LCFFs) are crucial components for multisupply systems as interfaces between different voltage islands. The proposed energy-efficient LCFFs reduce the power consumption of clock networks with dual-edge triggering, support sleep mode of power management mechanisms with data retention, and have symmetry in setup times and insensitivity to output parasitics. With all these features, the proposed LCFFs have 19% and 38% lower power-delay product than the conventional LCFF, as demonstrated by postlayout simulation results.

In this paper, we propose a dual-edge triggered and dual-Vth level converting flip-flop (LCFF). The LCFF utilizes many energy-saving features that can be used in a multi-Vdd and multi-Vth system. A novel power-aware latch structure is designed to eliminate the internal power during transition. When operated in sleep mode, the power-aware latch is switch to low-leakage mode and still retain its data. Experimental results show that the proposed LCFF has the lowest PDP among compared FFs.

In this paper, we propose two novel dual edge-triggered flip-flops. One design eliminates redundant transitions of internal nodes when current data is the same as the previous one. This has the least power delay product compared to other dual edge-triggered flip-flops in all range of possible data switching activity and its delay is also the smallest. The other proposed flip-flop disables internal clocked transistors. When data switching activity is within 20%, it has the least power consumption.

In this paper, we present a novel design methodology for synthesizing multiple configurations (or modes) into a single programmable core that can be used in embedded systems. Recent portable applications require reconfigurability of a system along with efficiency in terms of power, performance, and area. The field programmable gate arrays (FPGAs) provide a reconfigurable platform; however, they are slower in speed with significantly higher power and area than achievable by a customized application-specific integrated circuits (ASIC). Implementation of a system in either FPGA or ASIC represents a trade-off between programmability and design efficiency. In this work, we have developed techniques to realize efficient reconfigurable cores for a set of user-specified applications. The resultant system, named asmultimodesystem, can easily switch configurations throughout the set of configurations it is designed for. A data flow graph transformation method coupled with efficient scheduling and allocation is used to automatically synthesize aMulti-Modesystem from its behavior-level specifications. Experimental results on several applications demonstrate that our implementations can achieve about 60X power reduction on average and run 3.5X faster over corresponding FPGA implementations.

The polyphase channelizer is an important component of a subband adaptive filtering system. This paper presents an efficient hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer, integrating optimizations at algorithmic, architectural and circuit level. At the algorithm level, a computationally efficient structure is derived. Tradeoffs between hardware complexity and system performance are explored during the fixed-point modeling of the system. A computational complexity reduction technique is also employed to reduce the complexity of the hardware architecture. Circuit-level optimizations, including an efficient commutator implementation, dual-VDD scheme and novel level-converting flip-flops, are also integrated. Simulation results show that the design consumes 352 mW power with system throughput of 480 million samples per second (MSPS). A test chip has been submitted for fabrication to validate the proposed hardware architecture and VLSI design techniques.

The state dependence of leakage can be exploited to obtain modest leakage savings in complementary metal-oxide-semiconductor (CMOS) circuits. However, one can modify circuits considering state dependence and achieve larger savings. We identify a low-leakage state and insert leakage-control transistors only where needed. Leakage levels are on the order of 35% to 90% lower than those obtained by state dependence alone. Using a modified standard-cell-design flow, area overhead for combinational logic was found to be on the order of 18%. The proposed technique minimizes performance impact, does not require multiple-threshold voltages, and supports a standard-cell-design flow.

We present a high-level synthesis technique targeting low power consumption for data-dominated applications. We have used a statistical estimation technique to obtain the switching activity of modules when sharing of computing resources are required in a design. The technique enables us to understand the switching behavior under resource sharing. Using the relationship between switching power and resource sharing thus obtained, we developed scheduling and allocation algorithms to reduce the data path switching power. Experiments performed on various examples show up to 49% improvement in power reduction under resource constraints.