We present the first pin-count-aware optimization approach for test data delivery over a network-on-chip (NoC). Our approach addresses the key issue of optimal utilization of the limited I/O resources provided by automated test equipment (ATE) to keep test time and test cost under control. By co-optimizing core test scheduling and pin assignment to access points, test cost can be lowered by reducing test time for a given pin budget, or by reducing the number of test pins without impacting test time. To further improve resource utilization, we consider the use of MISRs for compacting the test responses of embedded cores. We show how the optimization framework can be extended to include power constraints during test application. Experimental results for ITC'02 test benchmarks demonstrate that pin-count-aware co-optimization leads to shorter test times for a given pin-count budget and fewer pins for a given test-time budget. Comparisons with dedicated bus-based test-access mechanism designs and a baseline heuristic method are presented; our results demonstrate the benefits of the co-optimization method for NoC-based test access. The results also highlight the advantages of the proposed use of output compaction and the impact of power constraints on the optimized test schedule and test-access architecture.

We present two test-data delivery optimization algorithms for system-on-chip (SoC) designs with hundreds of cores, where a network-on-chip (NoC) is used as the interconnection fabric. We first present an effective algorithm based on a subset-sum formulation to solve the test-delivery problem in NOCs with arbitrary topology that use dedicated routing. We further propose an algorithm for the important class of NOCs with grid topology and XY routing. The proposed algorithm is the first to cooptimize the number of access points, access-point locations, pin distribution to access points, and assignment of cores to access points for optimal test resource utilization of such NOCs. Test-time minimization is modeled as an NoC partitioning problem and solved with dynamic programming in polynomial time. Both the proposed methods yield high-quality results and are scalable to large SOCs with many cores. We present results on synthetic grid topology NoC-based SOCs constructed using cores from the ITC'02 benchmark, and demonstrate the scalability of our approach for two SOCs of the future, one with nearly 1000 cores and the other with 1600 cores. Test scheduling under power constraints is also incorporated in the optimization framework.

We present the first pin-count-aware optimization approach for test data delivery over a network-on-chip (NoC). By co-optimizing core test scheduling and pin assignment to access points, the limited I/O resources provided by automated test equipment (ATE) can be used more effectively. This approach allows us to lower test cost by reducing test time for a given pin budget, or by reducing the number of test pins without impacting test time. To further improve resource utilization, we consider the use of MISRs for compacting the test responses of embedded cores. Experimental results for ITC'02 test benchmarks demonstrate that pin-count-aware co-optimization leads to shorter test times for a given pin-count budget and fewer pins for a given test-time budget. The results also highlight the advantages of the proposed use of output compaction.

We present a test-data delivery optimization algorithm for system-on-chip (SOC) designs with hundreds of cores, where a network-on-chip (NOC) is used as the interconnection fabric. The proposed algorithm is the first to co-optimize the number of access points, access-point locations, pin distribution to access points, and assignment of cores to access points for optimal test resource utilization. Test-time minimization for grid-based NOCs is modeled as an NOC partitioning problem and solved with dynamic programming in polynomial time. The proposed method yields high-quality results that are comparable to integer linear programming (ILP), but unlike ILP, it is scalable to large SOCs with many cores. We present results on synthetic NOC-based SOCs constructed using cores from the ITC'02 benchmark, and demonstrate the scalability of our approach for two SOCs of the future, one with nearly 1,000 cores and the other with 1,600 cores.

This paper presents a highly effective compactor architecture for processing test responses with a high percentage of x-values. The key component is a hierarchical configurable masking register, which allows the compactor to dynamically adapt to and provide excellent performance over a wide range of x-densities. A major contribution of this paper is a technique that enables the efficient loading of the x-masking data into the masking logic in a parallel fashion using the scan chains. A method for eliminating the requirement for dedicated mask control signals using automated test equipment timing flexibility is also presented. The proposed compactor is especially suited to multisite testing. Experiments with industrial designs show that the proposed compactor enables compaction ratios exceeding 200x.

We present a new compactor architecture for extreme compaction of test responses with a high percentage of x-values. The test response data is compacted into a single, 1-bit wide bit stream. A major contribution of this work is a new technique to efficiently load x-masking data into a masking logic. A method eliminating the need for explicit mask control signals using ATE timing flexibility is also introduced. The proposed compactor can efficiently be employed in multi-chip testing. Experiments with industrial designs show that the proposed compactor enables compaction ratios exceeding 200x.

In this paper the design of error detection circuits for split-parity codes is investigated. In a split-parity code the linear parity bit is split into two nonlinear check bits. Split-parity codes, like parity codes, detect all odd errors with certainty; all even errors - which remain undetected by parity - are detected with a probability of 50%. It is shown that a large variety of split-parity codes exist which can be utilized for the optimization of error detection circuits with respect to area and error detection probability. It is demonstrated that split-parity codes are a cost-effective possibility to design error detection circuits.

In this paper we present a method for compacting test response data without the need for additional X-masking logic by using the timing flexibility of modern automatic test equipment (ATE). In our design the test response is compacted by several multiple input shift registers without feedback (NF-MISR). The shift registers are driven by a clock which is k times faster than the slower test clock of the scan chains. For each test clock cycle only one out of the k different outputs of each shift register is evaluated by the ATE. To mitigate the negative effects of consecutive X values within the scan chains, a permutation of the NF-MISR inputs is periodically applied. Thus, no additional external control signals or test set dependent control logic is required. The possibilities of an implementation on a Verigy ATE will be described. The presented results for three industrial circuits demonstrate the effectiveness of the proposed approach in comparison to a commercial ATPG tool.

This paper solves the problem of minimizing triple bit error miscorrection for single-error-correcting, double-error-detecting codes (SEC-DED codes) which are used to protect all kinds of memory against errors. A lower bound for triple bit error miscorrection for the widely used class of odd-weight column codes is derived and actual codes which are very close to that theoretical bound are presented. Surprisingly, significantly better results are obtained with shortened generalized Hamming codes. An optimal (39,32)-SEC-DED code with 32 information bits and 7 control bits is determined which has the lowest risk of triple bit miscorrection of any possible linear (39,32)-code. It is shown how codes with 64 and 128 information bits with significantly lower triple bit miscorrection probability than currently used codes can be derived from that code.The new codes also feature adjacent double bit error correction capabilities (SEC-DED-DAEC codes). Employing them in a SEC-DED-DAEC checker reduces the risk of miscorrecting non-adjacent double bit errors by 27-34% compared to the best codes known.

This paper introduces the concept of utilizing the timing flexibility of automatic test equipment (ATE) when designing X-tolerant test compactors. Redundant information is generated by the compactor and transferred to the ATE at a frequency k times higher than the scan shift frequency. This technique is different than current X-tolerant compactors where the necessary redundant information is generated on additional compactor outputs. If the Compactor design can take into account the ATE capabilities, the knowledge of the redundancy can be efficiently used. The ATE will select the relevant information out of the compacted test response, which then leads to a reduction of the ATE compare data by a factor k. In the best case this method can be applied without extra costs related to the higher frequency. The benefit of this approach is a higher parallel test factor due to the reduced number of output pins. This paper explains the capabilities of the employed ATE which need to be taken into account when designing an X-tolerant compactor using a higher output data rate. The method is also demonstrated on a shift register which works at a multiple of the scan shift frequency.