Article ATPG based on a novel grid-addressable latch element Share on Authors: Susheel J. Chandra CrossCheck Technology Inc., 2833 Junction Ave., Suite 100, San Jose, CA CrossCheck Technology Inc., 2833 Junction Ave., Suite 100, San Jose, CAView Profile , Tom Ferry CrossCheck Technology Inc., 2833 Junction Ave., Suite 100, San Jose, CA CrossCheck Technology Inc., 2833 Junction Ave., Suite 100, San Jose, CAView Profile , Tushar Gheewala CrossCheck Technology Inc., 2833 Junction Ave., Suite 100, San Jose, CA CrossCheck Technology Inc., 2833 Junction Ave., Suite 100, San Jose, CAView Profile , Kerry Pierce CrossCheck Technology Inc., 2833 Junction Ave., Suite 100, San Jose, CA CrossCheck Technology Inc., 2833 Junction Ave., Suite 100, San Jose, CAView Profile Authors Info & Claims DAC '91: Proceedings of the 28th ACM/IEEE Design Automation ConferenceJune 1991 Pages 282–286https://doi.org/10.1145/127601.127681Published:01 June 1991 20citation162DownloadsMetricsTotal Citations20Total Downloads162Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

The CrossCheck technique is beginning to gain acceptance as an effective low-cost solution to the ASIC testability problem. The technique provides massive observability by embedding test circuitry into the ASIC device. This allows highly accurate defect modeling and simulation with less computational resources than conventional techniques. This paper describes CrossCheck test technology and present results on its application to real-life designs. All these designs are sequential in nature with multiple, gated and asynchronous clocks. Bridging, comprehensive (opens and shorts) as well as conventional stuck-at I/O fault coverage, and CPU time and memory requirements are presented.>

The authors address the problem of accurate logic simulation in the presence of unknowns. Algorithms to perform exact simulation using high-level descriptions are presented. The complexity of these algorithms is shown to be considerably less than that of existing algorithms. An analysis of realistic programmable logic arrays (PLAs) and some random functions is used to compare the complexity of the two algorithms presented. Data on the SN74181 ALU suggest that function blocks of similar size can be easily dealt with. The feasibility of the approach is demonstrated by a programmed implementation of the algorithms as part of a high-level test generation system.>

A brief description is given of the CrossCheck test technology which provides the fundamental basis for this work. The authors present a practical analysis of transistor-level defects which result in accurate defect models in comparison to conventional fault models. The embedded test technology and accurate defect models are combined to form a high-quality test environment which is used to implement a high-performance test generation system. The authors present results on five ISCAS sequential benchmark circuits and two real designs. These results indicate that, in the presence of the embedded test electronics, test generation and fault simulation are considerably faster and test quality is substantially improved.>

The results of an extensive study of five existing testability measures when used to aid heuristics for automatic test pattern generation algorithms are presented. Each measure was evaluated using over 60000 faults in circuits of varying size and complexity. The performance of these measures was rated using several different criteria. Based on these results the performance of a composite test generation strategy that uses multiple guidance heuristics was evaluated. The results indicate that this strategy not only provides better fault coverage but also reduces the average time taken to generate a test or determine that a given fault is undetectable.>

The availability of low-cost, high-performance, general-purpose parallel machines has made parallel processing viable for the development of CAD (computer-aided design) applications. The authors identify the key issues that surface when an attempt is made to parallelize the test-generation process. They illustrate how different test-generation strategies can be mapped onto different classes of parallel machines, including loosely coupled distributed systems, distributed-memory systems with message-passing architectures, and tightly coupled multiprocessor systems with shared global memory. Parallel test generation using a single heuristic and using multiple heuristics is considered. The performance of these mapping strategies is predicted by using uniprocessor turnaround times and an estimate of the communication delays.>

Given a combinational network and a specific stuck-at fault to be detected, there are several approaches to generating a test vector. However, most of these approaches fail to exploit the hierarchy inherent in any complex digital design. This paper presents a hierarchical approach to test vector generation. HIPODEM: A test generation system based on this approach is presented. General procedures to perform forward implication and backtracing in a hierarchical framework are discussed in detail. Experimental results obtained from test runs on both flat-level and hierarchical circuits are compared. For the circuits tried, generating tests from a hierarchical description proved to be faster than doing it from a flat level description of the circuit.