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Michel Bardouillet

dblp:40/6876 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2006
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 100%
Network and information security
1 paper
Hardware security and side channels · 100%

Topics — the 1 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › memory interface
processor-memory interface
0.012006
A parallelized way to provide data encryption and integrity checking on a processor-memory bus · DAC 2006

Methods — techniques the papers use, named apart from their topics

parallel encryption · 0.1integrity checking · 0.1
YearPublicationVenuePosition
2006 A parallelized way to provide data encryption and integrity checking on a processor-memory bus
abstract
International audience
Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet, Albert Martinez
DAC5
2005 Hardware Engines for Bus Encryption: A Survey of Existing Techniques
abstract
The widening spectrum of applications and services provided by portable and embedded devices brings a new dimension of concerns in security. Most of those embedded systems (pay-TV, PDAs, mobile phones, etc.) make use of external memory. As a result, the main problem is that data and instructions are constantly exchanged between memory (RAM) and CPU in clear form on the bus. This memory may contain confidential data like commercial software or private contents, which either the end-user or the content provider is willing to protect. The paper describes the problem of processor-memory bus communications in this regard and the existing techniques applied to secure the communication channel through encryption. Performance overheads implied by those solutions are discussed extensively.
Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, C. Anguille, Michel Bardouillet, Christian Buatois, Jean-Baptiste Rigaud
DATE6