In this paper, we present a novel software tool called AVL Safety Extensions which is part of a tool framework for model-based automotive safety engineering. The tool framework supports a tool dependent methodology (TDM) which covers the left-hand V-model phases of ISO 26262-3 and ISO 26262-4 and requires the use of the language SSML (System Safety Modeling Language). The AVL Safety Extensions support safety engineers applying the TDM by creating consistent and complete work products and by simplifying and automating workflow steps. We present the AVL Safety Extensions in the context of the tool framework, the language SSML and the TDM focusing on the AVL Safety Extensions' capabilities for error model creation and visualization supporting safety analysis techniques such as FTA (Fault Tree Analysis) and FMEA (Failure Modes and Effects Analysis). Moreover, we illustrate the applicability of the presented approach using an industrial case study of hybrid electric vehicle development.

Electronic Control Units (ECUs) are implemented nowadays in safety-critical applications such as battery management or power control systems for hybrid vehicles. In this context, a critical product failure can harm people, environment or property and has therefore to be avoided. The challenge during the design of such components is to improve and guarantee the product quality while keeping flexibility for different variants and minimizing the development costs. We present in this paper first results of the newly started MEPAS project. The focus is set on improvements regarding requirements engineering as well as regarding the development of safety-relevant automotive embedded systems in the context of ISO 26262.

According to the standard IEC 61508 fault insertion testing is required for the verification of fail-safe systems. Usually these systems are realized with microcontrollers. Fail-safe systems based on a novel CPLD-based architecture require a different method to perform fault insertion testing than microcontroller-based systems. This paper describes a method to accomplish fault insertion testing of a system based on the novel CPLD-based architecture using the original system hardware. The goal is to verify the realized safety integrity measures of the system by inserting faults and observing the behavior of the system. The described method exploits the fact, that the system contains two channels, where both channels contain a CPLD. During a test one CPLD is configured using a modified programming file. This file is available after the compilation of a VHDL-description, which was modified using saboteurs or mutants. This allows injecting a fault into this CPLD. The other CPLD is configured as fault-free device. The entire system has to detect the injected fault using its safety integrity measures. Consequently it has to enter and/or maintain a safe state.