This paper presents a 16-bit, energy-efficient, fully dynamic successive-approximation-register (SAR) capacitance-to-digital converter (CDC) for single-ended capacitive sensors. A system-level correlated-double-sampling (CDS) scheme is proposed to suppress errors arising from comparator offset, low-frequency noise, and external interference. The delay time characteristics of the inverter-based amplifier (FIA) comparator are characterized for the first time, and an optimal delay time is determined through simulation. An LSB-repetition scheme improves low-noise performance. Dual digital-supply technique reduces the power consumption of the digital circuitry and also extend the delay time of digital delay elements with minimal power overhead, thereby improving energy efficiency. Fabricated in a 180-nm CMOS process, the CDC is validated using a capacitive MEMS pressure sensor, achieving a best resolution of 0.27 fF and a signal-to-noise ratio (SNR) of 82.6 dB among SAR CDCs. Consuming$2.85~\mu $W with a$56~\mu $s conversion time, it achieves a Walden figure-of-merit ($FoM_{w}$) of 15 fJ/step. The CDC attains a DNL of -0.76/+0.85 LSB and an INL of -9.16/+9.15 LSB without calibration. Experimental results demonstrate more than$16\times $improvement in interference rejection at 100 Hz and more than$7\times $improvement under 1000 Hz, compared to a non-CDS implementation.

This article presents a four-channel interface application-specific integrated circuit (ASIC) for infrared focal plane arrays (IRFPAs), where each channel integrates a programmable gain amplifier (PGA) with wide-range input common-mode adjustment capability and a 16-bit hybrid analog-to-digital converter (ADC) with resistor-sharing technique (RST). The flash stage of the ADC performs 5-bit most significant bits (MSBs) conversion, whose results are transferred to thermometer-coded capacitor array in the successive approximation register (SAR) stage, ensuring high linearity while maintaining conversion speed. This hybrid architecture of the ADC uses the RST by sharing the resistor ladder between the flash and SAR stages, reducing power consumption. The interface ASIC fabricated in the 180-nm CMOS technology achieves an input common-mode adjustment range of 0.169–3.269V. Operating at 2 MS/s with a 3.3-V supply, it achieves an 88.1-dB signal-to-noise-and-distortion ratio (SNDR) and consumes 13.97 mW/channel. The Schreier figure-of-merit (FoM) of the ADC reaches 171.2 dB/channel. Measured differential and integral nonlinearity (DNL/INL) are −0.38/+0.49 least significant bits (LSBs) and −2.2/+1.4 LSB, respectively.

This article presents a novel data acquisition system (DAS) designed for area-sensitive applications, including automotive instrumentation, launch vehicles, and satellites, which require efficient area utilization and full-swing input/output capabilities for diverse sensors. Traditional approaches to achieving full swing, such as using CMOS input transistors or generating negative voltage via charge pumps, either result in high harmonic distortion (HD) or complicate chip design. To address these challenges, we propose a complementary analog front-end (CAFE) that shifts the input signal by a fixed voltage, enabling operation in a more linear region while employing feedback to minimize HD. The system incorporates two analog-to-digital converters (ADCs) that convert the input signal and subtract the digital output of the common mode voltage ($V_{\text {CM}}$), facilitating effective data fusion for complete AD conversion. Fabricated using a 180-nm 1P5M BCD process, the DAS consumes 118.81 mW from a 5.0-V power supply, providing 64 channels in a compact area of$4.0\times 3.2$mm. At a sampling rate of 1 MS/s, it achieves an effective number of bits (ENoBs) of 13.16, with a power consumption of 1.856 mW per channel and a dynamic range of 83.3 dB, resulting in an impressive figure of merit per channel (FoMS/Ch) of 165.3 dB.

This paper presents an event-driven readout integrated circuit (ROIC) for imaging and target-tracking infrared focal plane arrays (IRFPAs). The pixel circuit consists of event detection (ED) and imaging and trace detection (ITD). Based on the dynamic vision sensor (DVS) structure, ED encodes the temporal changes of infrared radiation into synchronized 1.5-bit events and transmits them to the off-chip postprocessor. When a moving target is recognized, the region of interest (ROI) window address will be feedback to ROIC and read out the image and trace information provided by ITD, which is based on infinite impulse response in the analog domain. These absolute intensities and multi-frame fused trace allow the post-processor to complete high-accuracy agile action recognition. This ROIC provides a spatiotemporal redundant compression and energy-efficient solution for fast-moving object detection and analysis. A prototype based on a 16×16 array of 20 µm pixel-pitch has been fabricated using a 0.18 µm 1P5M CMOS process, consuming [email protected] event and image frame frequency. Detailed test and measurement results of the prototype are presented.

This paper presents a low-power and energy-efficient capacitance-to-digital converter (CDC) for a single-end sensor based on correlated double sampling (CDS) technology. The CDS is accomplished by two opposite conversions, which reuse the comparator, CSENS, and CDAC. The proposed CDC eliminates the parasitic-dependent error caused by the comparator’s offset without extra consumption through the CDS. The simulation results show that the CDC can eliminate low-frequency interference and achieve anti-common-mode interference capabilities similar to differential circuits. To achieve low noise and high energy efficiency, the CDC employs a floating inverter amplifier (FIA) as the pre-amplifier of the comparator. Implemented in a 0.18 μm CMOS process, it consumes 0.91 μW from a 1.2 V supply. The simulation results show an effective number of 11.69 bits and an energy efficiency of 27.5 fJ per conversion step.

This work presents an application specific integrated circuit (ASIC) working as an electrical vagus nerve stimulation (VNS) system targeting emerging VNS-based point-of-care treatments where such a system needs to be implanted within the human body. Implemented in a 180 nm Bipolar-CMOS-DMOS (BCD) process, the ASIC is capable of delivering accurate stimulation current, and can support stimulation voltages up to 15 V. Such a high voltage compatibility provides extra room for variances in tissue impedance under the same requested stimulation current. The design is tested with a commercial-grade platinum helical electrode, and shows a maximum output current of 7 mA when the electrode is submerged in phosphate-buffered saline (PBS), and a low standby power of$9.63\ \mu\mathrm{W}$. The low power, small area, high output current resolution, and process's compatibility with direct processor integration all make this design a promising candidate for a single-chip implanted VNS system.

A compact low-noise digital pixel with 15-bit pixel-level two-step analog-to-digital converter (ADC) is presented in this paper. The coarse quantization adopts a 10-bit pulse frequency modulation conversion with a proposed threephase charge-reset circuit. The charge-reset circuit reduces the reset noise charge which is the major noise of this pixel. The fine quantization is implemented by a 5-bit single-slope ADC. It reuses most of the coarse quantization circuit to realize high precision quantization in compact pixel. A 640×512 readout integrated circuit for infrared focal plane array with the 15μm pitch digital pixel is designed in the 0.18 μm1P5M CMOS process for verification. Post-layout simulation results of the digital pixel show that the RMS noise at maximum signal is 0.51LSB, and the integral nonlinearity is +2.3LSB/-3.0LSB. The power consumption per pixel is only 57. 2nW at 120fps.

This paper presents an uncooled infrared imager with flicker noise reduction, which is realized by the proposed phase difference modulation (PDM) method. The PDM method makes noise transfer function (NTF) generate a series of notches to reduce flicker noise. To realize PDM, a high-speed sub-frame readout circuit is proposed. The readout circuit has been manufactured and the output data is processed with FPGA. The measurement results show that the flicker noise power in the frequency range above 10Hz is reduced by 42% compared with traditional method at 60fps full image output rate, and the noise equivalent temperature difference (NETD) is reduced from 40mK to 34mK.

This paper presents a low-power readout circuit with 14-bit column-level extended-counting ADC for 17μm-pitch 1024 × 768 silicon diode uncooled infrared imagers. The ADC's coarse conversion adopts a current-mode DAC to feedback charge into a CTIA-based integrator during integration and the fine conversion is implemented by a SAR ADC after integration. A current self-compensator and a modified DAC are proposed to reduce more than 50% power of the overall integrator compared with conventional structure. The 1024 × 768 readout circuit has been fabricated in the 0.18 μm 1P5M CMOS process. Power consumption of the readout circuit is 104mW and each column ADC only consumes 15μW. Simulation results show that the RMS noise of the readout circuit is 0.9LSB and nonlinearity is 0.06% at 30fps.

A high-precision digital readout interface for a ±15g open-loop MEMS capacitive accelerometer is present in this paper. The differential capacitance resulting from input acceleration is picked up by a low-noise switch-capacitor (SC) charge sensitive amplifier (CSA) and further digitized by a 2nd-order Σ-Δ ADC after amplification. In order to reduce the nonlinearity of the open-loop accelerometer with high mechanical sensitivity, a digital nonlinearity calibration system is implemented on chip with a 320×8-bit embedded EEPROM for parameters storage. Newton-Raphson iteration algorithm is utilized for compensation parameter calculation, and serial processing as well as floatingpoint operation is used for hardware overhead reduction. The interface designed in a 0.35-μm 3.3V/14V embedded EEPROM CMOS process occupies 12.14 mm2and draws 11.1mA from a 3.3-V supply. The measured original nonlinearity of the accelerometer is 0.32%, while it is reduced to 0.084% after the compensation parameters are written into EEPROM. Moreover, the accelerometer system achieves a noise floor of 5.5μg/√Hz over a 200-Hz bandwidth and a bias instability (BI) of 5.13μg.

This paper introduces a digital readout integrated circuit (DROIC) for 320×256 target-tracking infrared focal plane arrays(IRFPAs). The circuit is based on a two-stage ADC, which implements 10-bit coarse quantization and 4-bit fine quantization, enabling high frame frequency trace detection. In addition, the locating and independent output of sensitive pixels are realized by a scanning function, which greatly reduces output frequency and power consumption. The proposed ROIC of 15μm pixel-pitch is fabricated using 55nm 1P6M CMOS process. The pixel circuit consumes 379nW. Frame frequency of the target-tracking mode is 1 kHz, the two-stage ADC has a nonlinearity of 0.06%.

This paper presents a 16-bit 64-channel 2-order incremental Σ-Δ ADC with an on-chip decimating filter for linear X-ray detector array. In order to achieve high-resolution and multi-channel integration, a series of coefficients for a 2-order Σ-Δ modulator are optimally designed which are based on time-domain relationship between the modulator input and output. Therefore, a decimating filter consists of only a counter and an integrator can be used to acquire Nyquist rate output. A residual error reduction method at the end of each conversion period is also proposed to refine the resolution of convertor by extending several clock cycles and reusing the same circuit modules. As a result, a high-resolution, small area cost and power efficient readout interface circuit (ROIC) is achieved. A prototype chip is designed in 0.18μm CMOS process. Simulation results reveal the ADC achieves ±0.5 LSB quantization error and 91.4 dB SNR within 1.9 kHz bandwidth, meanwhile, area of the decimating filter in single channel is only 42×90 μm2.

This paper presents a pixel-level ADC for 640×512 mid-wavelength infrared focal plane arrays. The pulse comparator for windowed signal used in the single-slope structure proposed in this work obtains lower power consumption and lower RMS noise than conventional designs. Moreover, by employing a novel low-load 3T NMOS memory structure, hardware cost can be reduced. The pixel circuit with 15μm-pitch has been designed in the 0.18um 1P6M CMOS process. Power consumption of the pixel-level ADC is 0.107μW and the charge handling capacity is 10Me-per pixel. Depending on the simulation results, an average output RMS noise of 2LSB and a maximum nonlinearity of 0.15% are demonstrated.

A novel fully-differential switched-capacitor interface using DC-blocking technique is presented for a ±30 g closed-loop capacitive micro-accelerometer. In view of the indispensable high-voltage feedback in a high-g large-mass closed-loop accelerometer resulting in a high power consumption, a charge sensitive amplifier with DC-blocking structure is utilized in the closed loop, separating the low-voltage sensing from high-voltage feedback and making most of loop modules work in the low-voltage domain. Moreover, owing to the DC-blocking structure, the switched-capacitor closed-loop system achieves a full-period feedback instead of the conventional time-multiplexing feedback, and the closed-loop system can therefore operate at a higher sampling frequency without increased working current, further reducing the aliasing noise. The interface designed in a 0.35 μm 3.3V/15V CMOS process occupies 9 mm2. The simulation results show that it consumes 12.77 mA from a 3.3-V supply and only 64.2 μA from a 15-V supply at a 1-MHz sampling clock, which is comparable to the power dissipation of low-g counterparts, and the dynamic range is 120.37 dB over a 200-Hz bandwidth.

This paper presents a high-precision, low temperature coefficient (TC) CMOS bandgap reference for high-performance multi-channel ADC working under wide temperature range. A piecewise curvature compensation technique is proposed to extend its operating temperature range and keep its low temperature coefficient. A ß-compensation technique is used to cancel the PTAT and non-PTAT spread of the output due to variation of β in the BJTs. Moreover, the trimming resistors are implemented to calibrate the 1st-order temperature coefficient and absolute value of the output voltage. The bandgap reference designed in 0.18μm CMOS process has a super low temperature coefficient of 2.1ppm/°C over a wide temperature of −55 ° C to 140 ° C, making it appropriate to provide reference voltage for a high-precision ADC.

A fully-differential open-loop switched capacitor interface is presented in this paper for a ±30 g capacitive micro-accelerometer. Considering that input common-mode feedback capacitors in a fully-differential charge sensitive amplifier increase the gain of noise, a full-swing input common-mode feedback scheme is proposed in this work to minimize the feedback capacitance and reduce the noise. Moreover, since flicker noise contributed by the output stage cannot be ignored in an ultra low-noise design, a novel low-noise fully-differential sample- and-hold circuit is proposed, which not only suppresses the flicker noise considerably but also has smaller output spikes with lower power dissipation. The interface implemented in a 0.35 μm CMOS process occupies 9 mm2 and consumes 8.11 mA from a 3.3-V supply at a sampling clock of 1 MHz. The sensor achieves 80.4 mV/g sensitivity, 10 μg/√Hz resolution and 112.2 dB dynamic range over a signal bandwidth of 200 Hz.

This paper presents a low-power 14-bit column-level ADC for 640×512 size uncooled infrared imager. A novel differential-ramp single-slope (DRSS) structure is proposed in this work, which achieves 2x faster conversion speed and 3dB higher SNR performance compared with classical single-slope scheme. Moreover, a novel low-power area-saving result-consistent coarse-fine TDC scheme is proposed. The sensor with 17μm pixel pitch has been realized in 0.5 μm 2P3M CMOS process and applied in the thermal imaging system. Power consumption of per ADC is 120 μW. Measurement results demonstrate an average output RMS noise of 0.5LSB and a maximum nonlinearity of 3LSB.

This paper presents a new low-power readout structure for 1024×6 infrared focal plane array with 1/2 sub-scan time-delay-integration (TDI) and delay-locked-loop-based (DLL-based) analog-to-digital (A/D) function. The circuit is of low power for its passive sampling, delay, and summation completed by capacitor array. Multiple-capacitor structure is also used to make the circuit suffer less from capacitor mismatch. 1/2 sub-scan function and the distribution of detector array contribute to higher resolution in the direction both along the track and across the track. And the TDI function is combined with A/D process in terms of circuit structure and timing sequence, reducing the noise and enhancing the frame rate. The 14-bit ADC is divided into coarse quantization part and fine quantization part. The former is a conventional 11-bit single-ramp ADC and the latter is realized by 8-phase clocks generated by DLL. This circuit also supports bidirectional scanning and two types of detectors whose photo-current flows into or out of the readout circuit.

A switched capacitor interface is presented in this paper for a ±50 g capacitive micro-accelerometer. In order to suppress the flicker noise of the frontend, a switched capacitor proportional-integral controller combined with a charge sensitive amplifier using correlated double sampling is proposed. The controller has a simple structure with minimized number of switches and cancels the offset of both the charge sensitive amplifier and itself. A delay buffer following the controller is used to generate a z-1/2delay and drive the middle plate of the sensing element. The interface is implemented in a 0.35 μm 3.3 V/15 V CMOS process and the area of the chip is 11.75 mm2. The fabricated prototype circuit operates under 15 V and 3.3 V supply at a sampling clock of 100 kHz. Meanwhile, a sensitivity of 99.7 mV/g is achieved with the bias instability of 200 μg. The dynamic range of the accelerometer is 106.16 dB over a signal bandwidth of 200 Hz.

A low-noise MEMS vibration gyroscope interface is presented in this paper. A novel capacitance to voltage (C/V) conversion structure is introduced, which consists of a fully differential capacitor bridge and an active filtering net. An auto-calibration method is proposed, which can compensate the gyroscope mismatch to less than 2fF. We use a multistage noise shaping (mash) sigma-delta modulator to convert the analog signal to bit stream. The input referred noise of C/V conversion stage is 0.63 aF/√Hz at 8 kHz in simulation. The chip converts sensor output into bit stream with 106dB dynamic range.

This paper presents a novel two-step pixel-level analog-to-digital converter (ADC) design, which is embedded in a 17μm-pitch pixel for Infrared Focal Plane Array (IRFPA). Digitization includes two successive steps: the first is reciprocal and the second linear. With the reciprocal conversion, a high dynamic range is achieved, and the linear conversion, on the other hand, guarantees a suitable frame rate. For verification, a 15-bit two-step ADC along with the correspondent readout modules has been designed in the 0.18μm CMOS technology. The readout circuit operates at the rate of 100fps with an ultra-low power consumption of 45.77nW per pixel.

This paper presents a low-noise single-ended open-loop switched-capacitor interface circuit in 0.35μm CMOS technology for a comb structure micro-accelerometer. Using correlated double sampling, the low-frequency noise of the charge sensitive amplifier and the gain stage is suppressed, whereas the noise of the sensor charging reference voltage and the sample-and-hold circuit which follows the gain stage contributes considerably to the total output noise. In order to optimize the noise performance, an on-chip reference voltage generator and a dual-sample-and-hold circuit are designed. A detailed noise analysis of the two blocks is also presented. The fabricated prototype interface circuit achieves a measured capacitive sensitivity of 734mV/pF with an input equivalent noise floor of 0.41aF/√Hz and a dynamic range of 119.93dB over a 200Hz bandwidth at 1MHz sampling frequency.

A two-stage charge sensitive amplifier architecture suitable for semiconductor radiation detector with large capacitance is proposed. The integration capacitor of the first stage can be made large to reduce gain sensibility to detector capacitance without any stability problem. Each stage uses a self-biased MOS transistor to discharge the integration capacitor. The self-bias circuit tracks process, temperature and supply voltage variations to make a relatively constant feedback resistor. This improves the gain linearity of the charge sensitive amplifier and the uniformity of multi-channel front-end electronics. The feasibility of the proposed circuit is verified by comparing the simulation results with the conventional one-stage charge sensitive amplifier and a two-stage structure with fixed-gate-voltage reset transistor. A prototype of 16-channel front-end circuit for electron collection designed in a 0.35μm CMOS technology has been measured. The area is 2.5×1.54mm2with 42 pads and the power dissipation is 60mW with power supplies of 2V and 5V.