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Ruibai Xu

dblp:401/6729 · DBLP profile ↗
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3ranked-venue papers
0as first author
3since 2021 · last 2026
0009-0003-1830-4483ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021Software engineering, systems software and programming languages · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Hardware accelerators and domain-specific architectures · 57% GPUs and heterogeneous computing · 25% Processor architecture and microarchitecture · 17%
Software engineering, system software, and programming languages
2 papers
Compilers and program optimization · 100%
Artificial intelligence
2 papers
Deep learning architectures and training · 100%

Topics — the 10 heaviest of 11, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › machine learning accelerator › transformer accelerator
attention acceleration
1.012026
FlashAttention-T: Towards Fully Tensorized Attention by Exploiting Tensor-Vector Parallelism · PPoPP 2026
GPUs and heterogeneous computing
GPU kernel optimization
1.012026
FlashAttention-T: Towards Fully Tensorized Attention by Exploiting Tensor-Vector Parallelism · PPoPP 2026
Hardware accelerators and domain-specific architectures
machine learning accelerator
1.012026
FlashAttention-T: Towards Fully Tensorized Attention by Exploiting Tensor-Vector Parallelism · PPoPP 2026
Compilers and program optimization
deep learning compiler
0.912025
Mosaic: Exploiting Instruction-Level Parallelism on Deep Learning Accelerators with iTex Tessellation · ASPLOS (2) 2025
Compilers and program optimization › domain-specific compilation
tensor algebra compilation
0.912025
QiMeng-Xpiler: Transcompiling Tensor Programs for Deep Learning Systems with a Neural-Symbolic Approach · OSDI 2025
Hardware accelerators and domain-specific architectures › machine learning accelerator
DNN accelerator
0.912025
Mosaic: Exploiting Instruction-Level Parallelism on Deep Learning Accelerators with iTex Tessellation · ASPLOS (2) 2025
Processor architecture and microarchitecture
instruction-level parallelism
0.912025
Mosaic: Exploiting Instruction-Level Parallelism on Deep Learning Accelerators with iTex Tessellation · ASPLOS (2) 2025
Machine learning › Deep learning architectures and training › attention mechanism
efficient attention
0.312026
FlashAttention-T: Towards Fully Tensorized Attention by Exploiting Tensor-Vector Parallelism · PPoPP 2026
Machine learning › Deep learning architectures and training › attention mechanism
transformer attention
0.312026
FlashAttention-T: Towards Fully Tensorized Attention by Exploiting Tensor-Vector Parallelism · PPoPP 2026
Machine learning › Deep learning architectures and training
deep learning systems
0.312025
QiMeng-Xpiler: Transcompiling Tensor Programs for Deep Learning Systems with a Neural-Symbolic Approach · OSDI 2025

Methods — techniques the papers use, named apart from their topics

tensor core utilization · 2.0kernel fusion · 2.0neural-symbolic approach · 1.7itex tessellation · 1.7instruction mapping · 1.7
YearPublicationVenuePosition
2026 FlashAttention-T: Towards Fully Tensorized Attention by Exploiting Tensor-Vector Parallelism
abstract
The attention mechanism is central to modern deep learning, particularly in large language models (LLMs), but suffers from quadratic computational complexity. To accelerate attention computation on GPUs, fused attention techniques (e.g., FlashAttention) consolidate the matrix multiplication (GEMM) and softmax computations into a single kernel. However, these operations remain computationally decoupled: the GEMM leverages high-performance tensor units (Tensor Cores), while the softmax executes on slower vector units (CUDA cores). This imbalance induces severe vector intervals—periods where tensor units sit idle awaiting vector unit completion—significantly underutilizing tensor units. Furthermore, ongoing hardware advancements delivering faster tensor units exacerbate this bottleneck.
Jianxing Xu, Yuanbo Wen 0001, Jun Bi, Ruibai Xu, Guanglin Xu, Rui Zhang 0040, Wei Li 0008, Ling Li 0001, Tianshi Chen 0002, Qi Guo 0001, Yunji Chen
PPoPP4
2025 Mosaic: Exploiting Instruction-Level Parallelism on Deep Learning Accelerators with iTex Tessellation
abstract
Deep learning has achieved great success in numerous application areas at the cost of high computational complexity. To meet the ever-increasing computational demand, commodity hardware platforms (e.g., CPUs and GPUs) offer abundant computing resources including scalar, vector, and tensor units for deep learning that could execute in parallel. However, existing top-down tiling-based deep learning compilers often generate a homogeneous mapping from the given tensor computation task to hardware arithmetic instructions, failing to utilize different computing units simultaneously to achieve higher performance.
Jianxing Xu, Yuanbo Wen 0001, Ruibai Xu, Tingfeng Ruan, Jun Bi, Rui Zhang 0040, Xinkai Song, Yifan Hao 0001, Xing Hu 0001, Zidong Du, Chongqing Zhao, Jiang Jie, Qi Guo 0001
ASPLOS (2)4
2025 QiMeng-Xpiler: Transcompiling Tensor Programs for Deep Learning Systems with a Neural-Symbolic Approach
Shouyang Dong, Jun Bi, Jiaming Guo, Jianxing Xu, Ruibai Xu, Xinkai Song, Yifan Hao 0001, Ling Li 0001, Xuehai Zhou, Tianshi Chen 0002, Qi Guo 0001, Yunji Chen
OSDI6