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Rouzbeh Pirayadi

dblp:401/7851 · DBLP profile ↗
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2ranked-venue papers
1as first author
2since 2021 · last 2026
0009-0009-7026-0805ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 67% Processor architecture and microarchitecture · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › high-level synthesis
dynamically scheduled high-level synthesis
1.012026
Out with LSQs: Custom Circuits for Memory Access Reordering in Dynamic HLS · FPGA 2026
Electronic design automation
high-level synthesis
1.012026
Out with LSQs: Custom Circuits for Memory Access Reordering in Dynamic HLS · FPGA 2026
Processor architecture and microarchitecture
load/store queue
1.012026
Out with LSQs: Custom Circuits for Memory Access Reordering in Dynamic HLS · FPGA 2026
YearPublicationVenuePosition
2026 Out with LSQs: Custom Circuits for Memory Access Reordering in Dynamic HLS
Rouzbeh Pirayadi, Ayatallah Elakhras, Mirjana Stojilovic, Paolo Ienne
FPGA1
2024 A Built-In Integrated Rowhammer, Rowpress, and Leakage Detection Sensor for DRAM
abstract
The increasing density of DRAM chips has led to heightened susceptibility of memory cells to bit-flips. Rowhammer and Rowpress attacks on DRAMs have obtained significant attention due to their effectiveness in compromising system security and data integrity. A substantial portion of the previously proposed techniques for detecting rowhammer attacks focus on counting the number of row activations. However, these methods suffer from several limitations, including high overheads, lack of consideration for environmental conditions during DRAM operation, and limited tunability to detect rowpress attacks. To address these challenges, this work introduces a novel low-overhead built-in DRAM sensor designed specifically for detecting and locating rowhammer and rowpress attacks. The core idea behind the sensor is to utilize an additional non-operational DRAM sensor cell for each row. This auxiliary cell experiences the same potential rowhammer attacks as the other cells within that row. The sensor operates by controlling an extra precharged match-line based on the charge stored in the sensor cells. This sensor not only detects rowhammer attacks but also other environmental conditions that may impact DRAM cells retention time, such as temperature elevation or changes in operating voltage. Simulation results demonstrate that the proposed sensor detects all of the rowhammer attacks in the presence of process variation with a variance of up to 7.5% in circuit parameters. Furthermore, the area overhead introduced by the sensor remains about 1%, making it a promising solution for enhancing DRAM security with the minimum memory structure change.
Nezam Rohbani, Rouzbeh Pirayadi, Mohammad Arman Soleimani, Adrián Cristal, Osman S. Unsal, Hamid Sarbazi-Azad
ICCAD2