Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.

Chenpeng Wu

dblp:401/8026 · DBLP profile ↗
← Back
4ranked-venue papers
1as first author
4since 2021 · last 2026
0009-0006-9059-2776ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author · 3 since 2021Artificial intelligence and machine learning · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
GPUs and heterogeneous computing · 50% High-performance computing · 27% Hardware accelerators and domain-specific architectures · 23%
Artificial intelligence
1 paper
Efficient and distributed learning · 87% Deep learning architectures and training · 13%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
High-performance computing
stencil computation
1.012026
SPIDER: Unleashing Sparse Tensor Cores for Stencil Computation via Strided Swapping · PPoPP 2026
GPUs and heterogeneous computing › GPU computing
tensor cores
1.012026
SPIDER: Unleashing Sparse Tensor Cores for Stencil Computation via Strided Swapping · PPoPP 2026
Machine learning › Efficient and distributed learning
model compression
0.912025
Samoyeds: Accelerating MoE Models with Structured Sparsity Leveraging Sparse Tensor Cores · EuroSys 2025
Machine learning › Efficient and distributed learning › model compression › sparsity
structured sparsity
0.912025
Samoyeds: Accelerating MoE Models with Structured Sparsity Leveraging Sparse Tensor Cores · EuroSys 2025
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.912025
Samoyeds: Accelerating MoE Models with Structured Sparsity Leveraging Sparse Tensor Cores · EuroSys 2025
GPUs and heterogeneous computing › GPU computing › tensor cores
sparse tensor core
0.912025
Samoyeds: Accelerating MoE Models with Structured Sparsity Leveraging Sparse Tensor Cores · EuroSys 2025
Machine learning › Deep learning architectures and training
mixture of experts
0.312025
Samoyeds: Accelerating MoE Models with Structured Sparsity Leveraging Sparse Tensor Cores · EuroSys 2025

Methods — techniques the papers use, named apart from their topics

structured sparsity · 1.7sparsetensorcore · 1.7strided swapping · 1.0matrix multiplication transformation · 1.0
YearPublicationVenuePosition
2026 SPIDER: Unleashing Sparse Tensor Cores for Stencil Computation via Strided Swapping
abstract
Recent research has focused on accelerating stencil computations by exploiting emerging hardware like Tensor Cores. To leverage these accelerators, the stencil operation must be transformed to matrix multiplications. However, this transformation introduces undesired sparsity into the kernel matrix, leading to significant redundant computation.
Qiqi Gu 0002, Chenpeng Wu, Heng Shi 0005, Jianguo Yao 0002
PPoPP2
2026 Scaling NVMM-based file system on intensive shared file access
Qiqi Gu 0002, Chenpeng Wu, Bingheng Yan, Jianguo Yao 0002
J. Syst. Archit.2
2026 Deep generative framework for modeling single-cell drug perturbation response
Yongqing Zhang 0001, Chenpeng Wu, Zhigan Zhou, Zhengxiao Huang, Aochen Zhang, Zixuan Wang 0025
Neural Networks2
2025 Samoyeds: Accelerating MoE Models with Structured Sparsity Leveraging Sparse Tensor Cores
abstract
The escalating size of Mixture-of-Experts (MoE) based Large Language Models (LLMs) presents significant computational and memory challenges, necessitating innovative solutions to enhance efficiency without compromising model accuracy. Structured sparsity emerges as a compelling strategy to address these challenges by leveraging the emerging sparse computing hardware. Prior works mainly focus on the sparsity in model parameters, neglecting the inherent sparse patterns in activations. This oversight can lead to additional computational costs associated with activations, potentially resulting in suboptimal performance.
Chenpeng Wu, Qiqi Gu 0002, Heng Shi 0005, Jianguo Yao 0002, Haibing Guan
EuroSys1