Silicon photonics promises revolutionary advancements in communication and computing, leveraging the integration of photonic components onto silicon platforms. However, a critical challenge remains in achieving robust device performance under inevitable process variations inherent in CMOS fabrication. Existing design methodologies often fall short in assessing and mitigating the impact of these variations on device behavior, particularly in microring resonators (MRRs). To address this challenge, we present a novel, comprehensive workflow for designing process-variation-resilient silicon photonic MRRs, which we have integrated into a variation-aware design optimization framework called process variation analysis tool. Our approach seamlessly integrates process-variation robustness directly into the design phase, enabling early optimization of device performance characteristics. By exploring diverse process-variation scenarios, our workflow provides crucial insights into design tradeoffs and strategies for enhancing MRR robustness. Furthermore, we achieve this analysis efficiently through the use of compact models, striking a balance between accuracy and computational cost. This approach significantly reduces design cycles and resource requirements, offering a practical and cost-effective path toward optimizing MRR performance under real-world manufacturing conditions.