VLDB 2026 Research / reviewers in the wild / expert
Chris Petersen 0002
dblp:404/8560
· DBLP profile ↗
3ranked-venue papers
0as first author
2since 2021 · last 2023
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Memory systems · 59% Cloud and datacenter computing · 27% Storage systems · 14% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Cloud and datacenter computing › resource management
datacenter memory management |
0.7 | 1 | 2023 | TPP: Transparent Page Placement for CXL-Enabled Tiered-Memory · ASPLOS (3) 2023 |
Memory systems
page placement |
0.7 | 1 | 2023 | TPP: Transparent Page Placement for CXL-Enabled Tiered-Memory · ASPLOS (3) 2023 |
Memory systems › tiered memory
tiered memory management |
0.7 | 1 | 2023 | TPP: Transparent Page Placement for CXL-Enabled Tiered-Memory · ASPLOS (3) 2023 |
Storage systems
key-value storage |
0.3 | 1 | 2018 | Reducing DRAM footprint with NVM in facebook · EuroSys 2018 |
Memory systems
non-volatile memory |
0.1 | 1 | 2018 | Reducing DRAM footprint with NVM in facebook · EuroSys 2018 |
Methods — techniques the papers use, named apart from their topics
workload characterization · 0.7NVM block device integration · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | TPP: Transparent Page Placement for CXL-Enabled Tiered-MemoryabstractThe increasing demand for memory in hyperscale applications has led to memory becoming a large portion of the overall datacenter spend. The emergence of coherent interfaces like CXL enables main memory expansion and offers an efficient solution to this problem. In such systems, the main memory can constitute different memory technologies with varied characteristics. In this paper, we characterize memory usage patterns of a wide range of datacenter applications across the server fleet of Meta. We, therefore, demonstrate the opportunities to offload colder pages to slower memory tiers for these applications. Without efficient memory management, however, such systems can significantly degrade performance. Hasan Al Maruf, Hao Wang 0011, Abhishek Dhanotia, Johannes Weiner, Niket Agarwal, Pallab Bhattacharya, Chris Petersen 0002, Mosharaf Chowdhury, Shobhit O. Kanaujia, Prakash Chauhan |
ASPLOS (3) | 7 |
| 2022 | Supporting Massive DLRM Inference through Software Defined MemoryabstractDeep Learning Recommendation Models (DLRM) are widespread, account for a considerable data center footprint, and grow by more than 1.5x per year. With model size soon to be in terabytes range, leveraging Storage Class Memory (SCM) for inference enables lower power consumption. This paper evaluates the major challenges in extending the memory hierarchy to SCM for DLRM, and presents different techniques to improve performance through a Software Defined Memory. We show how underlying technologies such as Nand Flash and 3DXP differentiate, and relate to real world scenarios, enabling from 5% to 29% power savings. Ehsan K. Ardestani, Changkyu Kim, Luoshang Pan, Jens Axboe, Valmiki Rampersad, Banit Agrawal, Fuxun Yu, Ansha Yu, Trung Le 0003, Hector Yuen, Dheevatsa Mudigere, Shishir Juluri, Akshat Nanda, Manoj Wodekar, Krishnakumar Nair, Maxim Naumov, Chris Petersen 0002, Mikhail Smelyanskiy, Vijay Rao |
ICDCS | 18 |
| 2018 | Reducing DRAM footprint with NVM in facebookabstractPopular SSD-based key-value stores consume a large amount of DRAM in order to provide high-performance database operations. However, DRAM can be expensive for data center providers, especially given recent global supply shortages that have resulted in increasing DRAM costs. In this work, we design a key-value store, MyNVM, which leverages an NVM block device to reduce DRAM usage, and to reduce the total cost of ownership, while providing comparable latency and queries-per-second (QPS) as MyRocks on a server with a much larger amount of DRAM. Replacing DRAM with NVM introduces several challenges. In particular, NVM has limited read bandwidth, and it wears out quickly under a high write bandwidth. Assaf Eisenman, Darryl Gardner, Islam AbdelRahman, Jens Axboe, Siying Dong, Kim M. Hazelwood, Chris Petersen 0002, Asaf Cidon, Sachin Katti |
EuroSys | 7 |