This article presents the design and miniaturization of a wideband monolithic microwave integrated circuit (MMIC) fully distributed efficient power amplifier (FDEPA). Distributed structure arrangement has been applied not only on the auxiliary power amplifier (PA) but also for the main PA. Hence, complicated and bandwidth-limited input matching networks (IMNs) and phase alignment networks are replaced by artificial transmission lines (ATMLs) to simplify the design and save the chip area. At the same time, due to the wide bandwidth characteristic of the distributed main PA, the power back-off (PBO) bandwidth shows good results compared with the conventional single common-source PA arrangement. Besides, a compact wideband on-chip quadrature hybrid power splitter is employed to achieve reasonable power division and phase control. As a proof of concept, an FDEPA prototype has been designed and fabricated in a commercial 0.25-μm GaN-on-SiC process. The chip size is only 3.6 mm×2.55 mm with all the necessary components. From the measurement results, throughout the working band of 3.1-5.5 GHz (56% fractional bandwidth), 40.3-41.6 dBm saturation output power (Psat), namely 1.16-1.58 W/mm2power density are achieved. The associated saturation drain efficiency (DE) is around 46%-55.4% and the 9-dB PBO DE is around 30.3%-47.2%. Under 100-MHz orthogonal frequency division multiplexing (OFDM) signal excitation with 8.5-dB peak-to-average power ratio (PAPR), 29.3%-44.5% average DE has been observed for the whole operating band, while the adjacent channel power ratio (ACPR) is better than -46.2 dBc with the digital pre-distortion (DPD).

This paper presents the design and analysis of dual-band monolithic microwave integrated circuit (MMIC) switches, including a single pole double throw (SPDT) and a single pole four throw (SP4T). With a novel on-chip coupled-line (OCL) topology, the input signal can be switched into low- or high-band paths to create dual-band characteristics. By carefully selecting the electrical lengths of OCLs and device size for corresponding shunt-FETs, the operating frequencies for low- and high-bands can be determined. This brings about improved insertion loss (IL) and isolation (ISO) in a compact structure. With the proposed techniques, two switch prototypes have been designed and fabricated in a 0.25-$\mu $m GaN-on-SiC process for high-power capability. The SPDT consists of a low-band path and a high-band path. It achieves an average IL/ISO of 1.0/32 dB with the best input 1-dB compression points (IP1dB) of 37.2 dBm at a low-band of DC-15 GHz; and an average IL/ISO of 2.0/28.5 dB with the best IP1dB of 32.8 dBm at a high-band of 20-40 GHz, respectively. The return loss is better than 11 dB for each port. The SP4T achieves a fully integrated dual-band transmit/receive (T/R) switch with doubled low-/high-band paths. It shows an average IL/ISO of 2.26/27.5 dB with the best IP1dB of 31.2 dBm at a low-band of 5-15 GHz; and an average IL/ISO of 2.7/26.5 dB with the best IP1dB of 30 dBm at a high-band of 20-30 GHz have been achieved, respectively. Better than 11.3 dB return loss is obtained for each port. The chip sizes are$1.8\times 0.9$mm2 for the SPDT and$2.2\times 1.7$mm2 for the SP4T.

This article presents the design theory and implementation of a fully integrated coupled-line-based load-modulated balanced amplifier (CLLMBA) monolithic microwave integrated circuit (MMIC). To facilitate the design, a novel design method is proposed for the CLLMBA to precisely control the load modulation and output power back-off (OBO) level by arranging the current ratio among the control amplifier (CA) and balanced amplifiers (BAs). Moreover, to further expand the working bandwidth, the coupled-line couplers are adopted in the CLLMBA. Subsequently, the physical dimensions and operating conditions of the three sub-amplifiers are selected accurately based on load modulation analysis at the fundamental frequency. It leads to properly modulated impedances and cancels the output matching networks for sub-amplifiers. Besides, meandering lange couplers are adopted by double metal layers and air-bridges for a compact layout. To validate the proposed techniques, a CLLMBA prototype is implemented and fabricated in a commercial 0.25-$\mu $m GaN HEMT process with the die size of$3.1\times 2.3$mm2. The measurement result exhibits a 38.1-39.3 dBm saturated output power with a 45.8%-57.6% saturated drain efficiency (DE), and a 31.7%-42.3% DE at 10-dB OBO from 4 to 6 GHz. Furthermore, under a 100 MHz orthogonal frequency division multiplexing (OFDM) signal with 8.5 dB peak-to-average power ratio (PAPR), the average DE is 32.8%-40.6% and the adjacent channel leakage ratio (ACLR) after digital predistortion is better than −47.5 dBc.

This article presents a reference phase-shifting architecture (PSA) based on a phase-locked loop (PLL) and a digital-to-time converter (DTC). The double-path phase modulation scheme (DPMS) is proposed to accelerate the settling time of the reference PSA. Off-chip calibration is added to mitigate the effects of nonlinearity in the DPMS process. Additionally, a DTC with improved retiming is proposed to reduce phase-shifting errors. The reference PSA with the DPMS is designed and fabricated in a commercial 22-nm CMOS technology. It occupies 0.048-mm2 active area and 12.8-mW dc power consumption. It achieves a 360° phase tuning range with a resolution of 1.26° at 24.75 GHz. The rms and peak phase errors are 1.38° and 2.6°, respectively. With the proposed DPMS, the settling time of reference PSA is significantly reduced from more than$1~\mu $s to less than 10 ns. Moreover, the PLL with DTC features a phase noise of −112.1 dBc/Hz at 1-MHz offset from 24.75 GHz and a 79.7-fs jitter integrated from 10 kHz to 30 MHz with 250-MHz reference clock. The figure of merits (FoMs) of jitter versus power for the proposed PLL with and without DTC are −250.9 and −251.4 dB, respectively.

This brief presents a 360° tunable phase shifter (PS) with low phase error in a 0.25-$\mu $m GaN-on-SiC HEMT process. To achieve these features, the design incorporates two key innovations: a novel switched-bandpass phase-shifting cell (PSC) topology and a Q-learning-based optimization algorithm, both applied for the first time in monolithic microwave integrated circuit (MMIC) PS designs. The adverse effects of the charge trapping effect in GaN HEMT switches are mitigated by using a nonlinear equivalent circuit model. A PS prototype consisting of a fifth-order bandpass PSC and two third-order bandpass PSCs with a core area of$1.25\times 2.5$mm2 is designed, fabricated, and measured. Experimental results demonstrate a low rms phase error of less than 7.0°, along with high power linearity characterized by an IP$_{\mathrm {1\,dB}}$of 37 dBm and an IIP3 of 48 dBm, over a frequency range from 4.1 to 5.3 GHz.

In this article, a fully integrated 1.0–11.0-GHz wideband distributed power amplifier (DPA) monolithic microwave integrated circuit (MMIC) design is presented. Particularly, a coupled technique with bandpass (CTB) characteristic between the kth output node and the ($k+1$)th input node of amplification units (AUs) is adopted in the DPA design. It generates an additional signal reuse path (SRP) to reuse part of the output signal to superimpose the input signal, and then they will be reamplified to the output artificial transmission line (O-ATML). Moreover, due to the bandpass characteristic, the signal reuse can be manipulated to target the upper cutting edges of the working band to alleviate sharp gain and power roll-off. By carefully controlling the SRP, the overall gain, output power, and bandwidth are enhanced and extended. The systematic design approach for the DPA is detailed with circuit implementations and optimizations. To validate the proposed concept, a DPA MMIC prototype is implemented and fabricated in a commercial 0.25-$\mu $m gallium nitride (GaN)-on-silicon carbide (SiC) high-electron-mobility transistor (HEMT) process. It shows the compact layout within a die size of 3.36 mm2. Under 28-V VDD power supply, the measured results show a flat$14.8\pm 1.0$-dB small-signal gain with 10.0-GHz wide operating bandwidth and good impedance matching conditions. A saturated output power (${P} _{\text {sat}}$) of 7.25 W with peak power-added efficiency (PAE) exceeding 38.7% is achieved. The proposed DPA obtains around 1.54–2.16-W/mm2 power density associated with an average PAE of 34.5% over the entire frequency range.

This article presents a 3-stage millimeter-wave low-noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) design for broadband applications. The proposed structure consists of cascading common-source (CS) LNA with coupled interstage feedback (CIF) paths at the second and third stages. By tuning the coupling factor and the inductance of the CIF, enhanced overall gain and extended working bandwidth can be achieved simultaneously. The proposed CIF formed by a simple on-chip edge-coupled parallel metal-lines features small size and high flexibility. To facilitate circuit design and optimization, an equivalent circuit for the proposed CIF structure is developed. Besides, to address the trade-off between impedance matching and noise performance, a noise matching strategy focusing more on higher frequencies is presented to achieve good noise performance. With the proposed techniques, an LNA prototype is demonstrated in a commercial 0.15-$\mu \text{m}$GaAs E-mode pHEMT process. The fabricated LNA has a die size of 1.15 mm2 and DC power consumption of 109 mW. The measurement results show a peak gain of 25.6 dB with a 3-dB bandwidth of 9~42 GHz, the minimal noise figure (NF) of 1.91 dB, a group delay of 68.7± 20.5 ps, and 20.8 dBm best OIP3 under 2.0-V VDD.

In this paper, a 2-stage compact wideband low-noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) with multiple resistive feedback (MRFB) is presented. From the DC point of view, the proposed MRFB functions as a self-biasing structure to bias transistors in the optimal condition, improving the noise figure (NF) and linearity. Meanwhile, by employing MRFB with source degeneration and input inductor, the proposed LNA achieves wideband flat gain at the AC side. In comparison with traditional topologies, a wide bandwidth of more than 11.5 GHz with low noise figure of less than 2.5 dB can be achieved. To verify the proposed LNA structure, a chip prototype is fabricated in a 0.15-$\mu \text{m}$GaAs E-mode pHEMT process with a compact die size of only 0.75 mm2 including all the testing pads. From the measurement results, the proposed LNA circuit features a 1.0 to 12.5 GHz 3-dB working bandwidth (172% fractional bandwidth), 23.6 peak gain, 1.51 dB minimum NF, 66.7± 15 ps group delay, and 24.3/12.6 dBm best OIP3/OP1dB, respectively. The total DC power is around 87.5 mW from a single 2.5-V power supply.

Wireless chip area network which enables wireless communication among chips fosters development in wireless communication and it is envisioned that future hardware system and developmental functionality will require multimaterial. However, the traditional system architecture is limited by channel bandwidth-limited interfaces, throughput, delay, and power consumption and as a result limits the efficiency and system performance. Wireless interconnect has been proposed to overcome scalability and performance limitations of multihop wired architectures. Characterization and modeling of channel become more important for specification of choice of modulation or demodulation techniques, channel bandwidths, and other mitigation techniques for channel distortion and interference such as equalization. This paper presents an analytical channel model for characterization, modeling, and analysis of wireless chip-to-chip or interchip interconnects in wireless chip area network with a particular focus on large-scale analysis. The proposed model accounts for both static and dynamic channel losses/attenuation in high-speed systems. Simulation and evaluation of the model with experimental data conducted in a computer desktop casing depict that proposed model matched measurement data very closely. The transmission of EM waves via a medium introduces molecular absorption due to various molecules within the material substance. This model is a representative of channel loss profile in wireless chip-area-network communication and good for future electronic circuits and high-speed systems design.